It's helpful to look at a common curve of a FET Drain Current (Id) vs Drain to Source voltage (Vds) with a fixed Vgs.
If the transistor was a perfect current source you would see a constant Id vs Vds (in saturation), instead there is an imperfect slope, making it not constant but close to the ideal. This non-ideal behavior can be modeled by looking at the Id equation $$I_{ds} = (k'/2)*(W/L)*(Vgs-Vt)^2*(1+\lambda*V_{ds})$$
Note, the equation is to a first order, valid after the triode region (as you mentioned) and in the saturation region. In the triode region, it behaves closer to a variable linear resistor, rather than a fixed resistor.
With a diode configuration, as in your example, we are guaranteed to be in the saturation region, so we don't need to worry about the triode region.
Since it has a current and a voltage, we should be able to extract an approximate resistance out of that. We could take a fixed point along the vds curve (for a fixed vgs, both are the same when connected in a diode config), and just take Vds/Id to get the resistance Rds. But any point along the vds will give a slightly different value, hence the non constant resistance (and non ideal current).
We can look at the derivative of the first equation*, to get a measure of the variation of that current with respect to changing vds, hence vgs (as they are tied). The derivative gives $$\frac{
\partial I_{ds}} {\partial V_{gs}} = (k'/2)*(W/L)*(Vgs-Vt))$$ Then the ratio of voltage across the device (drain source) divided by the current out (Ids) is $$r_{ds} \approx 1/{(k'/2)*(W/L)}$$ ignoring the constant transcendence, parameter you can see Resistance is proportional to length over width. Often in switching applications, you use larger than min W's to minimize the resistance. And in output gain devices you might see larger Ls to increase output impedance. Also, it is common to stack more than one device in current source applications, since this will actually increase resistance dramatically and improve the current source closer to an ideal.
*note, that the simplified first order derivation ignored the lambda term, which can be used to derive a more accurate on resistance (as lambda directly relates the slope of Ids to Vds) for non diode connected Fets.
** The rds derivation above is for 1/gm, which is a low impedance in the diode configuration, and often not used for high gain amplifiers. Instead the gate voltage will be biased separately from drain.
*** Looking back at your question,the relation to channel (width) as above equation showed is narrower channel (width), means higher R.
