MOSFET in saturation mode

A MOSFET in saturation mode behaves like a constant current source but a current source has infinite output resistance. To make it work like an active load instead of a passive load like a resistor we short-circuit gate and drain terminals and it goes directly into saturation.

Then how does it work as a finite resistance of 100k$$\\Omega\$$ in saturation mode?

Are these properties because of physical parameters? Or is it because we are working with MOSFET for digital IC and their behavior varies for analog and digital?

Talking about narrower channel, can I relate it to the W/L ratio of MOSFET. And is there any expression (mathematical) that can relate W/L ratio to the resistance? (Where W and L are width and length of the channel respectively.

I've attached the image of the book where this point has been mentioned.

• Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking.
– Community
Sep 7, 2021 at 6:51
• Would Electrical Engineering be a better home for this question? Sep 7, 2021 at 7:08
• Read the paragraph! "The load resistor is DESIGNED to have a narrower channel, so its Ron is MUCH GREATER". Properties are determined by the design, by varying its physical parameters. (So, try this with an IRF540 and you'll see something very different from 100 kilohms!) Sep 7, 2021 at 12:16
• wiki.analog.com/university/courses/electronics/… may be of help to you.
– Syed
Sep 7, 2021 at 12:29
• ittc.ku.edu/~jstiles/412/handouts/…
– G36
Sep 7, 2021 at 17:19

It's helpful to look at a common curve of a FET Drain Current (Id) vs Drain to Source voltage (Vds) with a fixed Vgs.

If the transistor was a perfect current source you would see a constant Id vs Vds (in saturation), instead there is an imperfect slope, making it not constant but close to the ideal. This non-ideal behavior can be modeled by looking at the Id equation $$I_{ds} = (k'/2)*(W/L)*(Vgs-Vt)^2*(1+\lambda*V_{ds})$$ Note, the equation is to a first order, valid after the triode region (as you mentioned) and in the saturation region. In the triode region, it behaves closer to a variable linear resistor, rather than a fixed resistor. With a diode configuration, as in your example, we are guaranteed to be in the saturation region, so we don't need to worry about the triode region.

Since it has a current and a voltage, we should be able to extract an approximate resistance out of that. We could take a fixed point along the vds curve (for a fixed vgs, both are the same when connected in a diode config), and just take Vds/Id to get the resistance Rds. But any point along the vds will give a slightly different value, hence the non constant resistance (and non ideal current).

We can look at the derivative of the first equation*, to get a measure of the variation of that current with respect to changing vds, hence vgs (as they are tied). The derivative gives $$\frac{ \partial I_{ds}} {\partial V_{gs}} = (k'/2)*(W/L)*(Vgs-Vt))$$ Then the ratio of voltage across the device (drain source) divided by the current out (Ids) is $$r_{ds} \approx 1/{(k'/2)*(W/L)}$$ ignoring the constant transcendence, parameter you can see Resistance is proportional to length over width. Often in switching applications, you use larger than min W's to minimize the resistance. And in output gain devices you might see larger Ls to increase output impedance. Also, it is common to stack more than one device in current source applications, since this will actually increase resistance dramatically and improve the current source closer to an ideal.

*note, that the simplified first order derivation ignored the lambda term, which can be used to derive a more accurate on resistance (as lambda directly relates the slope of Ids to Vds) for non diode connected Fets.

** The rds derivation above is for 1/gm, which is a low impedance in the diode configuration, and often not used for high gain amplifiers. Instead the gate voltage will be biased separately from drain.

*** Looking back at your question,the relation to channel (width) as above equation showed is narrower channel (width), means higher R.

• Thanks you. Really appreciate your help. Sep 8, 2021 at 13:35