What does "leading-edge blanking" do exactly?

Question

This below-highlighted block is in the L6562A PFC controller. In its application note is mentioned that the CS pin is equipped with 200 ns leading-edge blanking to improve noise immunity. What is it and how does it work? And what is that input for?

Answer 1

A switching converter is a noise source in essence: any time you activate a power switch on or off, you have multiple events going on like spurious oscillations, narrow spikes and so on. Very often, these events are of short duration and harmless to operations. However, their amplitude can sometimes be high enough to false-trip some of the control circuit protections and provoke an erratic behavior if not properly treated.

The typical example is the drain node of a boost converter for instance. When the power switch turns on, then the parasitic capacitance lumped at the drain is brutally discharged to ground. This capacitance is made of several contributors like the MOSFET \$C_{oss}\$, the diode capacitance or the inter-turn capacitance of the inductor for instance. The brutal discharge of the cap. together with gate-source current can be seen as a sharp current spike in the source then transformed in voltage by the sense resistor:

This spike by its high amplitude can cheat the internal current-sense comparator and affect the on-time duration, wrongly reducing the conduction time to a very narrow duration. When the UC1846 or UC384x went out, UNITRODE was recommending a front-end \$RC\$ filter inserted between the sense resistance and the current sense pin:

This filter did a good job but was also introducing some delay and could hamper the reaction time bringing a large peak current overshoot in fault conditions. I remember UNITRODE was using a 1k/470-pF \$RC\$ network.

Rather than using this external network, designers later on came up with the idea of blinding the current-sense comparator during a certain time, until the spike disappears. This is the idea behind the leading-edge blanking (LEB) circuit introduced in integrated circuits:

The above image shows a flyback converter and a sense resistor: when the latch instructs the switch to turn on, the series switch \$S_2\$ opens while \$S_1\$ closes: the current-sense input is firmly decoupled from the current-sense pin. After a certain moment - called the LEB duration - \$S_1\$ opens while \$S_2\$ closes, transmitting the current-sense information now cleaned-up from the spike to the comparator which can observe a nice signal. Typical LEB duration for 100-kHz controllers is a few hundreds of nanoseconds and can reduce for higher switching frequency.

If this circuit works well, it has the drawback to blind the controller during the LEB duration: what if the current runs away as soon as the power switch turns on? If you delay its opening by a few hundred of nanoseconds LEB to which you add the propagation delay (the sum of both forming the minimum \$t_{on}\$ a current-mode controller can go down to) then you may destroy the converter because it does not react quickly enough. The typical case is a secondary-side winding short circuit in a flyback converter. That is the reason why you often see another current-sense comparator having a higher threshold than the regular one but affected by a shorted LEB so that it can react in a much shorter time in case of malfunction.

Answer 2

That CS input is for current sensing, and to measure stably the current during when the switching transistor is on, the measurement signal is ignored for a moment when the transistor is turned on if there is noise or ringing artifacts that could trigger the set current limit prematurely.

Answer 3

The leading edge blanking is to ensure that the surge current into the gate (and through the source) of the MOSFET when driven by the GD pin, does not produce a "false" measurement of true drain current (as measured by the source resistor that feeds the CS pin).

The data sheet hints at what I've said above: -

Schematic: -

The critical parts are highlighted in red.