Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?


  • 1
    \$\begingroup\$ That sentence looks flawed if read alone, however what author actually intended is later on explained. There is no restriction like that on clock frequencies to cross a control signal of 1-bit. The only thumb rule is, the signal should be stable for at least 2 cycles in the destination clock domain if passed through a 2-flop synchronizer \$\endgroup\$
    – Mitu Raj
    Sep 7, 2021 at 12:55
  • \$\begingroup\$ That's just a rule of thumb. In theory any clock that is just slightly faster will be able to sample the slower signal at least once, but in real life you will want some margin and this author uses 1.5 for margin. \$\endgroup\$
    – Justme
    Sep 7, 2021 at 13:30
  • 1
    \$\begingroup\$ This thread discusses about the concept of sampling in Clock domain crossing, "why not Nyquist/Shannon". You can draw why x1.5 is for your case as well. \$\endgroup\$
    – jay
    Sep 7, 2021 at 14:14
  • \$\begingroup\$ @MituRaj I do not quite understand what it means by “three receiving clock edge" in which Litterick's paper does not really explain \$\endgroup\$
    – kevin998x
    Sep 7, 2021 at 15:55

3 Answers 3


Thanks for sharing the information. I enjoyed reading it.

I am no match for Nyquist, Shannon, or the authors of your reference documents. And, I thought I had to interpret x1.5 in a little different way. I forgot how I did, but I will try to explain. Please do not down vote or alter this, so we can promote independent thinking.

When Metastability is concerned, clock has the maximum of 1/2 cycle time for setup + hold, to be recorgnized as an edge, either rising or falling. Thus, rising edge is valid at a certain time after a valid falling edge, and vice versa. And we may apply the same setup and hold time to other signals in the Metastability perspective.

Thus, a signal from a clock domain's minimum residency is 1/2 cycle time of the clock. Let's the clock to be cycle time of Tcy, and the frequency of Fcy. And, we will analyze how a clock (domain) samples a signal from another clock domain.

When a signal was sampled (n0) at the earliest moment, 0xTcy, of the valid signal, the next sample (n1) window comes in duration of W1 from the current sample point,

1xTcy < W1 < 1.5xTcy --- (1)

When a signal is sampled at the latest moment, 0.5xTcy, of a valid signal, the next sample window comes in duration of W2,

W2 = W1 - 0.5xTcy => 0.5xTcy < W2 < 1xTcy ---(2)

Thus, the sampling frequency, f1, of window W1 is:

(1 / 1xTcy) > f1 > (1 / 1.5xTcy) ---(3)

The sampling frequency, f2, of window W2 is:

(1 / 0.5xTcy) > f2 > (1 / 1xTcy) ---(4)

From the relation of 1xTcy = 1/Fcy:

1xFcy > f1 > (1xFcy / 1.5) ---(3-1)
2xFcy > f2 > 1xFcy ---(4-1)

However, the reluctant sampling of 1.5xTcy misses sampling moment in the following cycles (n2, n3, ...). And, apparently;

A sampling window can be caught only by more than one shots (sampling) per a cycle. --- (5)

In order to find how many shots are needed, Let's call multiple of f1 fm1.

fm1 = f1 x M ---(6)

Now, eq(3) can be converted to:

(1xFcy x M) > (f1 x M) > (1xFcy / 1.5) x M ---(3-2)

From what we have found in (5), the lowest frequency has to be 1xFcy, or a shot per cycle. This leads to:

1xFcy = (1xFcy / 1.5) x M, and M = 1.5 ---(7)

Which resolves eq(3) to:

1.5xFcy > fm1 > 1xFcy ---(3-3)

Applying M to eq(4),

3xFcy > fm2 > 1.5xFcy ---(4-3)

The intersection of eq(3-3) and eq(4-3) occurs at 1.5xFcy, which tells;
Minimum of 1.5 times faster clock is required to sample a signal from another clock domain.

Concept of maximum setup and hold time for a clock domain.
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Concept of signal residency and interval, compared to clock cycle.
enter image description here

Early alignment: f1, W1, and fm1.
enter image description here

Late alignment: f2, W2, and fm2.
enter image description here

  • 1
    \$\begingroup\$ Good effort. Essentially, you are assuming setup & hold time are half the clock interval and thus must be 1.5x sampled signal rate. This is rarely the case however. \$\endgroup\$ Sep 8, 2021 at 16:48
  • \$\begingroup\$ @TonyStewartEE75, Not really that is what it is. Start from the definition of "Metastability", then look at it again. Still it does not touch your heart, let me know. :-) \$\endgroup\$
    – jay
    Sep 8, 2021 at 16:57
  • \$\begingroup\$ @TonyStewartEE75, It seems very few, or may not at all, people understand what I explained. From you, a smart one, I expected about 3 to 5 questions. The first step is as what I said "Start from the definition of Metastability". I will be offline for a while. Hope I see someday someone picks up the last question to be asked. \$\endgroup\$
    – jay
    Sep 8, 2021 at 20:01
  • \$\begingroup\$ wait, I could not differentiate between W1 and W2 inside the early and late alignment waveforms \$\endgroup\$
    – kevin998x
    Sep 9, 2021 at 3:35
  • \$\begingroup\$ @kevin998x Exactly, that is an important point how we reach to the conclusion. However, W1 and W2 have different reference points, 0xTcy & 0.5xTcy. Wonder if you were able to answer TonyStewart's question. The explanation is an abstraction. The answer to Tony's question is in the main text. I am not sure if I can explain it in a page, once a reader does not get it. \$\endgroup\$
    – jay
    Sep 9, 2021 at 17:57

There is no speed limit. They can be any ratio <=1. The 1.5x factor assumes the slow clock is perfectly 50% d.c. or 010101.

Consider only the fundamental freq. with the requirement being ; 1) no missing or extra cycle counts (or glitches). You must sample at least 50% faster, assuming the slow clock is perfectly 50% duty cycle.

Shannon's Theorem says you need 2x f to sample a sine fundamental to detect that frequency, but you do not recover the phase or amplitude perfectly, only detect that fundamental exists. Here, we sample with an edge and reset with an edge if about the same speed to detect if the slower input is high at least once during that interval. You won't get duty cycle or harmonic content. The 2 state single FF satisfies the Shannon criterion in the case of widely separated frequencies. Whereas, a dual FF edge trigger is used for “almost synchronous” or pleisiochronous clocks.

If a slow clock or bit of information clocks a 1 into a flip-flop and at any time that output is sent into a much faster bit stream, it resets the flip-flop at the same time as the read output latch to ensure it is always sent only once.

Anecdote. I used this method in '77 to send dual Servo Motor currents as digital bits using a voltage controlled one-shot as a 1kHz max tachometer signal into a 10 Mbps bit stream. It was sent some slow spare status bits, to get real-time feedback but with lower Bandwidth from a nuclear reactor to the control building over coax. It served to monitor servo friction in a robotic SCADA custom design I once did. (long time ago, far,far away) It appeared very accurate on analog edge-meters on the console. Without that async to sync, there were aliasing effects.

  • 2
    \$\begingroup\$ How does your answer relate to digital, clocked circuitry in an FPGA? The duty cycle of the clock can be arbitrary, because all logic only uses one of the edges to clock all flip-flops. DDR or double sampling with both edges is something different. \$\endgroup\$
    – asdfex
    Sep 7, 2021 at 17:52
  • \$\begingroup\$ If you assume 50% the question statement is valid as I said. If you assume arbitrary duty cycle then it is not valid and edge detection is required for both edges, which I also said. DDR is just a method of using 2 phase clocks for data and using 1 to decode both data transitions. \$\endgroup\$ Sep 7, 2021 at 18:16
  • \$\begingroup\$ Ahm, no. No part of the digital circuitry described in the linked text cares about the falling edge of the clock signals, everything happens with the rising edge only. \$\endgroup\$
    – asdfex
    Sep 8, 2021 at 15:56
  • \$\begingroup\$ @asdfex that's only your constraint just as is arbitrary d.c. . In that case, you need two rising edge flip flops at same or higher f, which contradicts the text in question and the assumptions I presumed to explain it. Let's see your answer. \$\endgroup\$ Sep 8, 2021 at 16:35
  • 1
    \$\begingroup\$ BTW all FF's use both states of the clock to create dual latches for S&H and register the output from a rising edge tinyurl.com/yhthyn2p @asdfex \$\endgroup\$ Sep 8, 2021 at 16:50

There is nothing special about the value of 1.5x. The author goes on to explain what he means a few paragraphs further down:

[This will work,] as long as the signal generated in [one] clock domain is wider than the cycle time of the [other] clock [...] A safe rule of thumb is the signal must be wider than 1.5x the cycle width of the destination clock

I.e., it must be guaranteed that the receiving clock is at least a little bit faster than the clock the signal originates from. In theory, 1.0001x would be good enough, but there are always sources of error:

  • all flip-flops have a setup and hold time, i.e. the signal must be stable for a certain time, often many percent of the cycle time. If the pulse is short, we might miss the setup time requirement in one cycle and miss the hold time requirement in the next cycle, effectively missing the whole pulse.

  • Oscillator frequencies vary with temperature and voltage and it's not guaranteed that both clocks vary in the same way and by the same amount throughout all operating conditions.

  • Clocks have jitter, i.e. clocks generated by a PLL can have period variations of 100 ps, which can easily be a couple of percent of the total clock period.

  • Switching times of flip-flops and all the transistors encountered during routing are not homogeneous. The transition time from high to low can well be different to the one from low to high. This results in the signal (that should be active for exactly one clock cycle) to be active for less or more than one clock period.

  • Switching thresholds of each and every transistor in the circuit is not equal, some may have a higher threshold and effectively shorten the length of the pulse.

  • All routing inside the chip depends strongly on the temperature and the current operating voltage in this specific location of the chip. If there is a lot of activity from other signals, voltage may drop locally and alter rise times and propagation delays, leading to a distorted signal length.

As a result, the receiving clock domain must be "quite a bit" faster than the source domain. A factor of 1.2 might be on the safe side, if operating conditions are favorable and the clock speeds are not close to the maximum the chip can deliver. I would be quite cautious if my clocks were this close in frequency and give the design a thorough test. With the cited factor of 1.5x you'll be on the safe side in any current FPGA no matter what happens. (Exceptions exist, e.g. ASICs built in custom processes can exhibit uncommon behaviors.)

  • \$\begingroup\$ The 3 clock problem stated by Mark Kittrick (Verilog ) was for memory accessed at 3 different rates, one being the same frequency which can be handled by a 2flop sync in each direction when stable yet with added MUX feedback if there is jitter. So 1.2 factor for Rx CLK in your answer or 1.5x pulse width at same frequency in Mark Kitterick's paper is not a barrier,just a timing margin that must accommodate all stress factors and worst case conditions in chip spec. \$\endgroup\$ Sep 8, 2021 at 22:27
  • \$\begingroup\$ @TonyStewartEE75 That's what I intended to describe, is there anything not clear enough? \$\endgroup\$
    – asdfex
    Sep 9, 2021 at 8:12

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