# Efficient discharge of capacitor voltage to 2-10 ohm DUT

I need to apply the voltage in a capacitor to a load (between 2 and 10 Ω) and need to have the most efficient and simple method to do so.

The goal is to apply power to a DUT (device under test), measure the energy applied to the DUT, and

• Have the highest possible amount of the energy stored in the capacitor reach the DUT.

• Drain the charge in the capacitor as quickly as possible.
It must never take longer than 10 ms (though I've found if it takes more than a few hundred µs it tends to be because the switching is too inefficient).

The capacitor is charged to specified voltage, disconnected from the power supply, and then a switch discharges the capacitor through a DUT (Device under Test).

Depending on specific test

• The capacitor can be charged from around 2 V to around 40 V,
• The capacitor can be from 0.68 µF to 100 µF

I am able to get 90-95% of the energy in the capacitor to the DUT using a IRLB8721PBF MOSFET.
Datasheet here - VDS - 30V, Ids - 62A, RDson - 9 mOhm, Qg - 8nC

The DUT (and a 0.05 Ω shunt) are in series between the capacitor and the drain of the MOSFET (low side switching). The source of the MOSFET is connected to 0 V. See schematic. Schematic is just the general concept - not the complete circuitry.

Questions:

• What principal parameters should I consider to determine how good a given transistor is for this application, or to determine the one that most closely meets my specifications ?

• Is a MOSFET the best solution. eg might a bipolar transistor be able to provide a better solution?

• If MOSFET is the way to go, does Vgs need to be at least Vth above Vds?

Mechanical switches aren't an option for the actual discharge switching.

I'm not too late to make small design changes around how the actual switching happens, I'm just paranoid that there is a better way to do this and that my tunnel vision on MOSFETs (specifically the one above) has blinded me from a better way.

• Is this the best MOSFET for this? - quite likely not and quite likely if I bothered to show you a better one then next week or next year I'll be wrong. This is not the place to ask shopping questions. You should probably put your shunt in the source of the MOSFET so it is ground referenced and will cause less of a measurement problem. Sep 7, 2021 at 18:42
• The MOSFET is reasonably good. with 8.7 milliohm Ohm resistance. It is unlikely that a sensible superior BJT solution is available. Thereare a number of parameters unspecified that make a quantitative answer impossible. Sep 16, 2021 at 12:17
• Non technical comments have been moved to chat. Question edited to make non-shopping in the eyes of the large majority if just maybe not all. Chat comments unlikely to be useful. here. Sep 19, 2021 at 12:13
• Question edited to remove shopping aspect - hopefully given a new life. Sep 19, 2021 at 12:17
• Note that the FET you mention has a Vdsmax of 30V but the possible test voltage range is stated to possibly reach 40V. Magic soke expected. Vdsmax FET should be usefully above Vdsmax. Sep 19, 2021 at 12:19

### The MOSFET

The $$\R_{DS(ON)}\$$ for this MOSFET is 9mΩ, already very good.

Importantly, it's much lower than the 50mΩ current sense resistor, making the sense resistor the most significant cause of energy loss during discharge (with a caveat described below).

To obtain this $$\R_{DS(ON)}\$$, though, you have to have to drive the gate way beyond the voltage $$\V_{GS(TH)} = 1.8V \$$ stated in the datasheet. In fact, on the first page of the datasheet, in the section entitled "Benefits", the phrase "Very Low RDS(on) at 4.5V VGS" is a pretty big hint.

On page 6 of the datasheet is this graph:

Here you can see that at room temperature, for this device to have an "on" resistance of less than 10mΩ, the required $$\V_{GS}\$$ is 5V, and it gets worse as temperature rises. To be certain, I would recommend a gate voltage of at least 10V.

So to answer your question "does Vgs need to be at least Vth above Vds", I have two things to say:

• No, you need at least 5V at the gate.
• The gate needs to be at least 5V higher in potential than the source, and $$\V_{DS}\$$ has nothing to do with it.

It's easy to apply a high voltage at the gate, but you also need to do it fast. The gate takes time to charge, and during that time the drain-to-source channel sits somewhere between high resistance (off) and 10mΩ (on), and is therefore dissipating power. Your goal is to keep the time spent in this middle ground as short as possible, which means charging the gate as quickly as possible.

The greatest impediment you face in this respect is any resistance that exists between the source of voltage that you intend to apply to the gate, and the gate itself. The gate is a capacitor, and together with the source resistance it forms a classic RC system, with an associated time constant R × C.

The datasheet tells us that the gate capacitance is around 1nF. So if your gate potential is derived from a source with 1kΩ of resistance, the time constant is:

$$\tau = 1k\Omega \times 1nF = 1\mu s$$

This is the amount of time it takes to charge to only 63% of the target source's voltage. Whatever your target voltage at the gate, if the source of that potential has a resistance of 1kΩ (such as the output of a typical opamp), you can expect that for 1µs the MOSFET will be a significant contributor to energy loss.

I'll leave you to decide how acceptable that is. The moral is that you may need to be very careful about how you "drive" the gate.

### The Shunt

With the shunt and the MOSFET there, totalling 60mΩ, and a DUT of 2Ω, the fraction of power delivered to the DUT (efficiency) will be (best case):

$$\frac{2\Omega}{2\Omega + 60m\Omega} = 97\%$$

This doesn't even account wiring resistance or capacitor ESR, which could be an additional few tens of milliohms. You won't be able to achieve better with this design, but you can factor this loss into your calculations.

### The Discharge

I think also that the extremely fast rise of current through the DUT will induce ringing, and will be easily coupled (both capacitively and inductively) into the gate drive circuitry, which could really mess things up. I advise that you keep that high-current loop well shielded (by using short, shielded cables) and keep loop area as small as as you can (don't use any long and/or widely separated traces/wires to close the loop).

Instead of a single large capacitor C, consider adding some smaller ceramics in parallel with it, say 1uF, 100nF and 10nF. This will improve its ability to respond to the sudden application of a heavy load, and may mitigate the ESR of C, another source of inefficiency. In fact, you can greatly improve the ESR of the capacitor by instead using multiple smaller capacitances in parallel.

Also, decouple your control circuitry with 100nF and 10nF capacitors - that sudden current spike will likely find its way to their otherwise clean voltage supply.

### The Charge

To initially charge the capacitor, you seem to be connecting it directly across the power supply. This is going to be a huge load on the supply, and a big cause for concern for anything else using it.

I recommend limiting charging current with a small resistor, say 10Ω, to keep it down to something more reasonable than "all-the-amps", and to prolong the life of the capacitor.

• Fantastic - thank you. Sep 8, 2021 at 16:39
• Your comments on ESR are spot on, we're already accounting for that separately. Message received on driving the gate and series resistance for the charging - we have that too (30Ω), I just neglected to put it in the sample circuit. Re: parallel capacitors, this may or may not be possible as it will be dictated by procedure I don't write, but I will do a workup and see if I can't improve the test by recommending a configuration like that if it ends up working out better. Thanks for your response! Sep 8, 2021 at 16:46

The purpose I gather is to measure the charge discharge energy efficient in a low ESR capacitor with a fixed resistor. Then compare at different V and load R values to see how it changes.

You might want to consider a constant charge CC circuit and constant discharge CC circuit so you get similar curves as in battery tests. Whatever load current you choose , select a FET with RdsOn < 1 % of your smallest load resistor using a a transistor or a switch with a cap across it to prevent bounce voltage on the gate.

You can simulate this in Falstad in short order by adding the 20 to 50mohm ESR if you choose your ps or any cap with ESR 100 to 200 uF caps. T=~20 us =ESR*C low ESR types (ballpark)

• Thanks for the input! What exactly is meant by constant charge/discharge CC circuit? Sep 7, 2021 at 22:05
• A constant current circuit. Like an LM317 with a series R= 1.25V / I between ADJ and OUT to charge and same for discharge. you just have 2 pins and it works down to 3V or so.. You could use a DPDT switch and use the same circuit CC to charge and discharge Sep 7, 2021 at 22:07