I trying to develop a discrete SR flip-flop into a serial in parallel out (SIPO) shift register, say 2 bits for the sake of learning. I don't have a clue how to proceed.

For the SR latch, I suppose I can use the simplest example on the internet as the one below.

enter image description here

The reason I chose not to use a two transistor NAND gate to construct the latch is that it requires four transistors.

How should I proceed from here to add clock to the above latch and convert it into a D flip-flop so that I can cascade them to create a shift register?

  • \$\begingroup\$ Do you know how to make a edge-triggered flip-flop from a level-sensitive latch? That would be your first step. \$\endgroup\$ Commented Sep 8, 2021 at 15:39
  • \$\begingroup\$ BTW they don't use RTL anymore \$\endgroup\$ Commented Sep 8, 2021 at 15:50
  • \$\begingroup\$ @jondoe If you want to do a shift register using BJTs, it will take a lot of them. Are you willing to consider it, seriously? \$\endgroup\$
    – jonk
    Commented Sep 8, 2021 at 19:46
  • \$\begingroup\$ I'm do not intend to physically build one, I really like to know how one would design it. \$\endgroup\$
    – jon doe
    Commented Sep 9, 2021 at 8:21

1 Answer 1


This is how CMOS D Flip Flops work (excluding S/R inputs) so you start from common technology. I could show a legacy mechanical toggle spring latch a little older than your Resistor Transistor Logic (RTL) , but not.

THe CMOS or Complementary MOS work well as high speed inverters and transmission gates shown as a SPST switch. When the input switch is closed a feedback inverter switch is also opened read to to latch the input , when the input opens and this switch closes. By using both edges of the CLK two such feedback latching stages are used to cascade the sampled input state. The sample is held by the CMOS rising edge (TTL uses falling edge with faster edges) when the input switch is open and the feedback switch latches type isolated input.

If you have any questions, study the simulation, stop it and see how the signal flows thru. Then you can select all, duplicate it , drag the blue copy to the right and edit>centre schematic to fit and then remove extra gen. Or you can select the D FF in a Blank screen option or select all [^A] and [DEL]

I showed a triangle input because after all logic transistors are analog devices with certain input characteristics. But I am not suggesting you use that, it's just that edges have a rise time, determined by R of driver and C of load.

enter image description here

These switches started with high resistance when the CD4000 family operated at high voltage and went higher with lower V+. But as the FET's became smaller and made with lower resistance, they were limited to 5V and about 50 Ohms. The same is true as with 25 ohm 3.3 or 3.6V logic.

I thought this would be more useful than trying to teach old technology.

  • 1
    \$\begingroup\$ Wow they use only NOT gates and switches in a D Flip-Flop, that's new information, thank you. \$\endgroup\$
    – jon doe
    Commented Sep 8, 2021 at 17:48

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