This is how CMOS D Flip Flops work (excluding S/R inputs) so you start from common technology. I could show a legacy mechanical toggle spring latch a little older than your Resistor Transistor Logic (RTL) , but not.
THe CMOS or Complementary MOS work well as high speed inverters and transmission gates shown as a SPST switch. When the input switch is closed a feedback inverter switch is also opened read to to latch the input , when the input opens and this switch closes. By using both edges of the CLK two such feedback latching stages are used to cascade the sampled input state. The sample is held by the CMOS rising edge (TTL uses falling edge with faster edges) when the input switch is open and the feedback switch latches type isolated input.
If you have any questions, study the simulation, stop it and see how the signal flows thru. Then you can select all, duplicate it , drag the blue copy to the right and edit>centre schematic to fit and then remove extra gen. Or you can select the D FF in a Blank screen option or select all [^A] and [DEL]
I showed a triangle input because after all logic transistors are analog devices with certain input characteristics. But I am not suggesting you use that, it's just that edges have a rise time, determined by R of driver and C of load.
These switches started with high resistance when the CD4000 family operated at high voltage and went higher with lower V+. But as the FET's became smaller and made with lower resistance, they were limited to 5V and about 50 Ohms. The same is true as with 25 ohm 3.3 or 3.6V logic.
I thought this would be more useful than trying to teach old technology.