As part of a project I have a 4 MHz pulse train output of a device with 50% duty cycle. I need a circuit which can turn on a relay if a pulse is missing. I can take care of the relay interfacing but need help with the detection part. I can tweak by using SPICE if I can find a generic topology. Is there stable a way to achieve this (for 4 MHz pulse train) without using an FPGA or a microcontroller? A diagram to work on would really help.

  • \$\begingroup\$ Look up "retriggerable multivibrator". You want one whose period is set slightly longer than 250 ns, so that if it ever times out, the output will go low, and you can activate your relay. \$\endgroup\$
    – Dave Tweed
    Commented Sep 9, 2021 at 13:49
  • \$\begingroup\$ A more complex, but potentially more accurate and reliable solution would involve a PLL. \$\endgroup\$
    – Dave Tweed
    Commented Sep 9, 2021 at 13:57
  • \$\begingroup\$ Thanks I will check out. Is there another name for the "retriggerable multivibrator"? Apparently cannot find such category name in vendors such as: uk.rs-online.com/web/c/semiconductors/logic-ics/… \$\endgroup\$
    – GNZ
    Commented Sep 9, 2021 at 13:59
  • \$\begingroup\$ I just plugged the phrase into Google, and immediately got this and this. Once you have specific part numbers, you can look them up at your favorite distributor. \$\endgroup\$
    – Dave Tweed
    Commented Sep 9, 2021 at 14:03
  • \$\begingroup\$ Thanks I found a DIP package one scribd.com/document/158711872/SN74LS123N-pdf cannot solder surface mount \$\endgroup\$
    – GNZ
    Commented Sep 9, 2021 at 14:07

2 Answers 2


I love this question.

My approach to a solution is to charge a capacitor slowly, and instantly and completely discharge it every time an input pulse arrives. I control the capacitor's charge rate so that, as long as it discharges with each incoming pulse, it never manages to charge sufficiently that its voltage exceeds the level required to be recognised as a logical high.

Here's the design:


simulate this circuit – Schematic created using CircuitLab

Q1 becomes a short circuit across C1, discharging it very quickly, every time its base goes high. When the base is low, following the falling edge of some incoming pulse, the capacitor is free to charge, and must charge at a rate which will cause it to exceed the input threshold voltage of the first inverter gate only if sufficient time has elapsed between incoming pulses.

"Sufficient" will be defined by the interval between the falling edge of an input pulse, and the rising edge of some input pulse following a "missing" one. We require the capacitor to reach about \$\frac{2}{3}\$ of its final voltage (\$V_{CC}\$) within that interval. However we also require that this threshold not be reached before an expected pulse arrives.

Here's a graph showing the interval (T) after which we may conclude that a pulse has not arrived in time:

enter image description here

I think that it's safe to choose a time constant (R1 × C1) in the vicinity of 250ns, giving rise to the values I've chosen for R1 and C1. Here I have made C1 significantly greater than the input capacitance of the inverter, so that I may disregard that gate's contribution to total capacitance.

It's possible that any old gate, like the inverters in a 74HC04, will work, but you'll get best results from a schmitt trigger device like a 74HC14 (for the first gate, at least), because you need the response to be a sharp transition, in spite of the relatively slow (analogue) rise of the input potential. You could also use schmitt NAND gates from a 74HC132.


Just a random idea: you can charge a capacitor (via appropriate resistance, calculated) and the capacitor will hold certain voltage. If there is a pulse missing, the capacitor will discharge more.

Could use op amp to isolate (buffer) signal from RC circuit not to charge it from the signal directly. A comparator can detect voltage drop on capacitor by comparing it to predefined voltage that it would drop to if the pulse is skipped. That comparator can output an interrupt for the MCU.

You will have to do some tweaking with capacitor's charging time after the skipped pulse etc. etc.

Okay, my 2-minute DIY solution resulted in me roughly sketching it in paint. Apologies for the quality, but we value idea over my drawing skills hopefully:

enter image description here

The only problematic moment is the initial charging which you may want to implement differently, it takes time to make up a solution, and I'm a terribly busy person (ha ha). The idea is that when pulse train begins, you want to have capacitor fully charged by the GPIO that will turn into input mode during pulse train. I think I should have put a high resistor on that line too.

Or, actually, the precharging circuit should be something else. I was also considering inverting the output of the buffer op amp so that when there is no signal, the output is high and the cap is charged by default and the whole high-low logic will simply be reversed.

By I digress, specifics are up to you to figure out. I propose the principle. Anyway (given we stick to my idea for this example), during signal low, the capacitor will partially discharge, but when the pulse is skipped, the cap will discharge more. So the input to the comparator will drop below estimated threshold and the comparator will change its state. You can treat it as an interrupt. Don't forget to recharge the capacitor to full again as it happens, because otherwise your capacitor will charge-discharge between different voltages after the first skipped pulse and will trigger interrupt literally on every pulse.


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