I'm trying to understand if I can use 4 x PCM4222 ADCs (datasheet) with the ADAT generator AL1401 (datasheet).
They would be working togheter using PCM audio mode, left-justified format, that both chips support.
I would use PCM4222 in "Normal mode" (Double and Quad Speed modes would produce sample rates not compatible with AL1401). The initial idea was that one of the four ADC would be set as Master, the other three would be set as Slave. There would be a master clock, at 256fS, feeding the MCKI input of the ADC. WDCLK and BCLK would then be provided by the Master ADC to the other chips.
AL1401 needs a single clock signal, WDCLK, since it generates its own BCLK internally (64*WDCLK, see page 4 on the datasheet).
But then, reading the PCM4222 datasheet, I noticed this (page 21):
the BCK clock output rate is fixed in Master mode, with the Normal mode being 128fS and the Double and Quad Speed modes being 64fS. In Slave Mode, a BCK clock input rate of 64fS or 128fS is recommended for Normal mode, while 64fS is recommended for Double and Quad Rate modes.
It means that the ADC configured as Master would output the data twice as fast as what AL1401 expects, since BCK is fixed at 128fS, am I right?
So what I'm thinking is, can I use all four PCM4222 configured as Slave, so that they all need a 64fS BCLK, just like what AL1401 expects?
If so, I would not have any Master device than provides all the timing, and I will need to generate all the clocks. The question is, can I generate BCLK and WDCLK from the master clock, simply dividing the clock multiple times using a flip-flop or similar?
What other aspects should I take into consideration?
thank you, and sorry for my poor english