# Is this actually a good CMOS NAND gate?

This is from www.electronics-tutorials.ws which I just discovered yesterday. The site has a plethora of electronics engineering content, more than I've ever seen from a free site.

I came across this diagram but it does not look right to me. First of all, all 3 transistors are an NMOS. Second of all, what's the point of having the top transistor permanently on? Just use a path to $$\V_{cc}\$$ . Third, if both bottom transistors are on, then you have a path from ground to output but you also have a path from $$\V_{cc}\$$ to output. That's called a short and is very dangerous and draws a huge power surge.

Is there something I'm not getting here? Does the diagram have a "simple typo" that explains everything?

I can't see how this is a valid CMOS design for a NAND gate. At the very least, the top transistor should be PMOS and fed one of the inputs so its not permanently on or off.

• Not very good. The pullup is an NMOS acting as a source follower (hopefully a weak one, i.e. a current source) : consider Vgs, and what that does to Vout high level. It'll also waste power when Vout is low. Sep 10, 2021 at 17:51
• It does not look like CMOS NAND but it looks like NMOS NAND. Sep 10, 2021 at 18:40