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This is from www.electronics-tutorials.ws which I just discovered yesterday. The site has a plethora of electronics engineering content, more than I've ever seen from a free site.

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I came across this diagram but it does not look right to me. First of all, all 3 transistors are an NMOS. Second of all, what's the point of having the top transistor permanently on? Just use a path to \$V_{cc}\$ . Third, if both bottom transistors are on, then you have a path from ground to output but you also have a path from \$V_{cc}\$ to output. That's called a short and is very dangerous and draws a huge power surge.

Is there something I'm not getting here? Does the diagram have a "simple typo" that explains everything?

I can't see how this is a valid CMOS design for a NAND gate. At the very least, the top transistor should be PMOS and fed one of the inputs so its not permanently on or off.

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    \$\begingroup\$ Not very good. The pullup is an NMOS acting as a source follower (hopefully a weak one, i.e. a current source) : consider Vgs, and what that does to Vout high level. It'll also waste power when Vout is low. \$\endgroup\$ Sep 10, 2021 at 17:51
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    \$\begingroup\$ It does not look like CMOS NAND but it looks like NMOS NAND. \$\endgroup\$
    – Justme
    Sep 10, 2021 at 18:40

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FET3 acts as a pull-up resistor and is designed to conduct an appropriate amount of current (a trade-off between speed and current consumption).

This is an NMOS gate, not a CMOS gate.

I believe there is an error in the symbol and text for FET3- it should be shown as a depletion-mode MOSFET rather then enhancement mode. As an enhancement-mode it will not fully pull up, but rather the pull-up current will peter out at around the threshold voltage, resulting in a nasty, slow, and incomplete voltage rise.

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