I'm trying to configure a Memory Interface Generator IP in Vivado. Somehow, the Block Automation doesn't work and I've to do it myself.

The board I'm using is the Arty A7 development board. It has a DDR3L SDRAM on it. The reference manual of the board states that the data width of the external memory is 16-bit. I also checked the schematic and saw that there are 16 pins for data transfers. See below.

Schematic Screenshot

Does the data width of an external memory is the same as the pins/lines used for the connection? What is the limit for it? From which part of the memory part datasheet can I determine this data width thing?


1 Answer 1


It reads in the documentation that the chip has a 16-bit wide bus and also if there are multiple chips they are still connected to same 16-bit wide bus, instead of making a wider 32-bit bus.

So yes, the data bus is 16-bit, and there are 16-bit chips there.

  • \$\begingroup\$ On which page is it written? \$\endgroup\$ Commented Sep 12, 2021 at 9:12
  • \$\begingroup\$ The DDR3 section of the Arty reference manual. \$\endgroup\$
    – Justme
    Commented Sep 12, 2021 at 10:07

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