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When a floating-gate transistor has no negative charge in the gate (i.e., it is erased), it conducts when the world-line voltage is applied to its gate terminal, pulling the bit-line to ground. Doesn't this mean that an erased cell represents a logical '0' rather than a '1'?

I browsed the web a bit and came across this lecture:

http://class.ece.iastate.edu/ee330/lectures/EE%20330%20Lect%2012%20Fall%202017.pdf

If you look at page 15 you can see an inverter on top of the bit line. Could this explain the discrepancy? Still, why is this inverter needed?

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When a floating-gate transistor has no negative charge in the gate (i.e., it is erased), it conducts when the world-line voltage is applied to its gate terminal, pulling the bit-line to ground. Doesn't this mean that an erased cell represents a logical '0' rather than a '1'?

No. Which voltage you interpret as 0 or 1 is completely up for interpretation. Humans tend to thing "higher voltage == 1", but there's no technical reason for that. You can map low voltage to 1 as much as you like, or you can map much larger blocks of cell states to blocks of bits:

In fact, for flash memory of any significant size, you'll find that error-correcting codes are used to allow for smaller cells whilst staying reliable. With that, there's code bits that get mapped to data bits in a block code – and how that code looks like defines how "block of flash memory cell states" map to "block of data bits"; this doesn't only involve arbitrary inversions (and non-inversions), but extends to non-systematic codes: It's pretty possible that if you change a single bit on e.g. an SSD, there's no single cell that always changes, regardless of the other bits in the block.

I'd recommend mentally separating "charge of a capacitor" from "bit": The bit's value is an interpretation of that charge, anyways.

And that's a pretty important property of flash memory: there's inherently a comparison of voltages / currents to a reference voltage/current, which is used to decide in which state the memory cell is when reading.

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    \$\begingroup\$ And then there are multi-level cells... \$\endgroup\$ Sep 14, 2021 at 11:34
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    \$\begingroup\$ @thebusybee exactly! That illustrates very nicely how "charge" needs to be interpreted to get "bit(s)"! \$\endgroup\$ Sep 14, 2021 at 11:54
  • \$\begingroup\$ @MarcusMüller well, as a student I've seen cases of negative logic (0 = high voltage, 1 = low voltage) maybe once or twice. All the digital electronics textbook I've studied assumed positive logic (including the chapters about memory devices), hence my confusion. Is it still correct to assume that voltage on the bitline will be HIGH if there's charge on the floating gate and LOW otherwise? \$\endgroup\$
    – Adrian
    Sep 14, 2021 at 13:56
  • \$\begingroup\$ no, it's not a correct assumption.It might be more common, but there's really no reason to assume HIGH=1, LOW=0. \$\endgroup\$ Sep 14, 2021 at 14:01
  • \$\begingroup\$ @MarcusMüller yes, yes, I get that. I was talking about voltages and setting conventions aside. As I understand it, the voltage on the bitline has to be 0 V if the transistor is conducting and VDD if it isn't... \$\endgroup\$
    – Adrian
    Sep 14, 2021 at 14:13

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