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I am designing a DDR3 interface to a Xilinx Kintex Ultrascale FPGA. The FPGA is connected to two separate DDR3 chips which share address, command, and control lines using flyby topology. I've attached links to the FPGA datasheet and the DDR3 IC datasheet below.

I've learned that best practice for routing DDR3 should keep the maximum skew between address, command, and control traces within +/- 25ps. Does this mean that the maximum skew between address pins on the same chip should be 25 ps, or that the overall maximum skew from the FPGA to the termination network should be 25 ps?

For example, lets say that the propagation delay from the FPGA to chip 1 on ADD0 is 150 ps, and the propagation delay from the FPGA to chip 1 on ADD1 is 185 ps. Is this acceptable as long as the total difference in propagation delay between ADD0 and ADD1 to the termination resistors is within 25 ps? My intuition tells me this is not okay because write-leveling compensates for propagation delay differences between separate byte lanes, but if the address bits on the same chip don't show up in the proper time window, there's nothing you can really do to fix that. I'd like to verify my intuition though.

Thanks in advance.

FPGA datasheet: https://www.xilinx.com/support/documentation/data_sheets/ds890-ultrascale-overview.pdf

DDR3 datasheet: https://www.issi.com/WW/pdf/43-46TR16512B-81024BL.pdf

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Leveling compensates for the difference between the address/control lines, and the DQS group.

So, for the ICs that are later on the flyby bus, the data is launched later so it arrives with the same timing respective to the control lines, and data from those chips is latched later -- so the timing at each IC is the same.

Since we're adding arbitrary delays to each DQS group anyway, we can also calibrate that for the actual length of the DQS/DQ traces, so if a group has longer traces, the delay added through leveling is smaller.

Leveling is limited by the input clock though: the DLLs cannot shift by more than a fixed angle, AFAIK 180 degrees. The leveling is also different for read and write, because the length of the DQS group traces is added to the length of the address/command traces for reads, and subtracted for writes.

So the goal is to make the DQS groups as short as possible because the longest DQS group defines the clock limit. Depending on the controller implementation, there may also be a requirement that the address/control lines to the first IC must be longer than the DQS group going to it so the delay for write leveling doesn't become negative -- ideally it would not be much longer, because the distance between the first and last IC again places a limit on frequency.

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