I am designing a DDR3 interface to a Xilinx Kintex Ultrascale FPGA. The FPGA is connected to two separate DDR3 chips which share address, command, and control lines using flyby topology. I've attached links to the FPGA datasheet and the DDR3 IC datasheet below.
I've learned that best practice for routing DDR3 should keep the maximum skew between address, command, and control traces within +/- 25ps. Does this mean that the maximum skew between address pins on the same chip should be 25 ps, or that the overall maximum skew from the FPGA to the termination network should be 25 ps?
For example, lets say that the propagation delay from the FPGA to chip 1 on ADD0 is 150 ps, and the propagation delay from the FPGA to chip 1 on ADD1 is 185 ps. Is this acceptable as long as the total difference in propagation delay between ADD0 and ADD1 to the termination resistors is within 25 ps? My intuition tells me this is not okay because write-leveling compensates for propagation delay differences between separate byte lanes, but if the address bits on the same chip don't show up in the proper time window, there's nothing you can really do to fix that. I'd like to verify my intuition though.
Thanks in advance.
DDR3 datasheet: https://www.issi.com/WW/pdf/43-46TR16512B-81024BL.pdf