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While I'm aware this is somewhat a copy of this question, I've not been more than a browser of any part of stack exchange, and so I couldn't ask this in a comment replying to @supercat 's answer. The question and answer are quite a few years old at this point and I'm looking for a more modern point of view. I am also just a first year CE undergrad so I don't quite know how to connect supercat's points to my exact use case.

So to be clear then about my question, I don't quite understand why exactly the instruction decoding logic takes any significant amount of power, or why that logic hasn't seen equivalent speed and efficiency performance to the rest of the CPU. Along with those things I'm looking for clarification on, I also wonder in what scenarios x86, or more broadly CISC in general, would be more efficient thanks to its increased number and complexity of instructions, and not in spite of that. Do more complex tasks like folding simulations or whatever else supercomputers get used for get to take advantage of those extra complex instructions and see performance gains that make up for the die space and power spent on the decoding and caching? If so are there any average consumer tasks that benefit similarly? And if not, is there some paper that details some agreed upon inherent inefficiencies with x86?

And for more clarification on why I'm asking, if that would help anyone answering to know how to phrase an answer: With the release of the Apple M1, we now have a better example than ever for the power and thermal savings allowed by ARM instruction sets. In looking into this, I've found that the M1 clearly consumes less power and outputs less heat at the same or better performance than competing x86 CPUs from AMD or Intel. However in attempting to control what exactly to compare it to to eliminate as many variables as possible aside from the instruction set, I found that the M1 is manufactured on TSMC's 5nm node, and therefore has no direct equivalent in the competition, since AMD has yet to release anything based on this process. So now, as I attempt to back up my claim that x86 is inefficient for the average consumer as a result of its complexity in a paper for my Engineering English course(1), I have a significant lack of concrete data that I feel measurably backs up that claim. So I at least wanted some more educated logic to ground my argument in.


    1: I include this because I'd like to make it clear that this is not data that will be used to back any major decision or design choice, and so educated guesses and speculation are certainly appreciated where there is no hard evidence, even more so if you let me know what your experience is so I can give provide ethos for that information. It's just a short, basic paper analyzing the design of something and making a claim about it (good, bad, and why it is, why the claim matters) and this was the only thing that came to mind when deciding what to write about.
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  • \$\begingroup\$ It will take quite a lot of thorough-going research of existing materials and similarly time-consuming analysis to prepare a comprehensive answer. I've personally been involved both at MIPS (R2000 days) and at Intel (tasked to find silicon bugs in their chipsets) and just thinking about this question makes my mind reel at the work involved in developing the required comprehensive view so that one could begin to organize and then produce a sound argument. You haven't even touched a finger yet on many issues I see needing time. And I'm yet quite ignorant compared to many. \$\endgroup\$
    – jonk
    Commented Sep 14, 2021 at 1:13
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    \$\begingroup\$ Worse, you really should communicate with various experts -- those willing to make themselves available to you -- in order to make sure that you've got all the right marbles in play and in the right proportions. You don't have to agree with those experts. But you absolutely should communicate with them about what you are learning and pulling together, as you go. The whole process will be a difficult one. And you'd have to find a way to compare apples to apples (sorry about the M1 pun.) \$\endgroup\$
    – jonk
    Commented Sep 14, 2021 at 1:16
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    \$\begingroup\$ "I've found that the M1 clearly consumes less power and outputs less heat at the same or better performance than competing x86 CPUs from AMD or Intel." - I hate statements like that. Apart from the numerous confounding factors, without actual numbers it's meaningless. According to Passmark, the M1 has average CPU mark of 15165 with typical power consumption of 15.1W, while the AMD Ryzen 7 PRO 5850U has average CPU mark of 19461 and typically draws 15W. \$\endgroup\$ Commented Sep 14, 2021 at 2:22
  • \$\begingroup\$ @jonk Its not nearly such a complex paper. I chose a topic far broader than the requirements (750-1100 words) allow for, which in retrospect, was a mistake. The prompt was to describe and critically analyze the design of a technology that "helps to structure everyday life" and the report should advance or support a position. So as it stands I think the best course of action is to change my claim to something far simpler and more easily supported. The point was to show that we can analyze a design and its effects, not to specifically go after instruction set inefficiencies. \$\endgroup\$ Commented Sep 16, 2021 at 1:57

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Question is somewhat faulty, since in practice power efficiency between ARM and x86, when fabricated on similar logic nodes, and targeting similar power points is very similar. See:

Our methodical investigation demonstrates the role of ISA in modern microprocessors’ performance and energy efficiency. We find that ARM and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the other. The ISA being RISC or CISC seems irrelevant.

https://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-power-struggles.pdf

However, the devil is in the details, and there are some differences that are worth discussing.

So to be clear then about my question, I don't quite understand why exactly the instruction decoding logic takes any significant amount of power, or why that logic hasn't seen equivalent speed and efficiency performance to the rest of the CPU.

The main disadvantage of x86 is the variable length instruction encoding. That means that each instruction depends on the one before it. On most ARM flavors, instructions are 32 bits long, so to decode 3 instructions you fetch 96 bits. On x86, you typically fetch a fixed number of bytes (often 16 bytes), decode as much as you can, and depending on what was in those bytes you'll get an unpredictable number of instructions back. There are workarounds for this like uop caches, but the underlying decode process is less efficient, especially if you need to decode lots of instructions in parallel.

How much this matters depends a lot on what you are doing. The above link looks at relatively low power processors, so the ability to decode huge numbers of instructions in parallel is not so critical. For other examples like the very wide M1, this is more awkward for x86 to match, although not impossible.

I also wonder in what scenarios x86, or more broadly CISC in general, would be more efficient thanks to its increased number and complexity of instructions, and not in spite of that.

Complexity of instructions is essentially irrelevant, and anyway, both ARM and x86 use extremely complex instructions. The classic ARMv4/v5 for example had instructions that could microcode in dozens of individual operations. I would not compare ISAs based on abstract concepts like complexity.

With the release of the Apple M1, we now have a better example than ever for the power and thermal savings allowed by ARM instruction sets. In looking into this, I've found that the M1 clearly consumes less power and outputs less heat at the same or better performance than competing x86 CPUs from AMD or Intel. However in attempting to control what exactly to compare it to to eliminate as many variables as possible aside from the instruction set, I found that the M1 is manufactured on TSMC's 5nm node, and therefore has no direct equivalent in the competition, since AMD has yet to release anything based on this process.

Besides fabrication node, this is a poor way to assess ISAs because the M1 also targets a different perf/efficiency operating point than typical x86 processors (which are expected to run on high power desktop and server systems, not just mobile devices). So you're comparing processors made for different purposes and on different technologies and trying to attribute differences to ISA. Does that really make sense?

So now, as I attempt to back up my claim that x86 is inefficient for the average consumer as a result of its complexity in a paper for my Engineering English course(1), I have a significant lack of concrete data that I feel measurably backs up that claim.

I wouldn't make that claim. The complexity of an ISA is a nebulous, difficult to quantify thing, and for the most part not very important. Plus both of the ISAs you are comparing are extremely complex (compare for example to more traditional RISC like MIPS for example), so the underlying differences are not so great. The combination of hard to measure, not very important and not very large makes for a hard to write paper. I would refocus your paper more narrowly on some aspect of the ISA that you can more easily measure, such as number of registers, instruction encoding, or vector extensions.

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  • \$\begingroup\$ To be clear about comparisons, I would have been looking at ryzen mobile CPUs with similar TDP targets. I wouldn't compare a 5950x with an M1, I'm not quite that inexperienced. Beyond that, this is way more than I was expecting from an answer but exactly what I was looking for really! thanks for the help!! \$\endgroup\$ Commented Sep 16, 2021 at 1:38
  • \$\begingroup\$ @NotThatSmart You can set the TDP of a processor to almost anything by changing voltage and frequency, but each processor is still designed with some specific perfect/efficiency where they are optimal. Comparing a higher power processor like a 5950x to a lower power one, even at equal TDP, doesn't make much sense. The processor targeting lower power should almost always be more efficient. \$\endgroup\$ Commented Sep 16, 2021 at 3:36
  • \$\begingroup\$ Variable length instruction encoding isn't a problem by itself, but becomes one when the encoding is not designed for efficient parallel decoding of multiple instructions. And nobody back in the 70s thought it would be necessary in some future descendant of 8086. \$\endgroup\$ Commented Mar 1, 2023 at 16:59

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