I have declared a string in the testbench code. However, I find that it is not simple to assign value to it. Here is the test code:
process
variable str : string(1 to 64);
begin
str := "hello world";
report str;
wait;
end process;
Why can't string contain index 0 in it? Also, how can I assign a string of any length to this variable since it won't be easy to make every string I assign to it, equal 64 characters by putting in white spaces.
EDIT:
This is what I came up with at the end, is there a simpler way to do this in VHDL?
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
entity experiment_4 is
end entity;
architecture beh of experiment_4 is
procedure write_string(strout: out string; constant strin: in string) is
variable str : string(strout'range);
variable l,r: integer;
begin
if strin'length > strout'length then
assert false report "the specified string cannot fit into the specified variable" severity failure;
else
for i in strout'range loop
strout(i) := ' ';
end loop;
strout(strin'range) := strin;
end if;
end procedure;
begin
process
variable str : string(1 to 64);
begin
write_string(str, "hello world");
report str;
wait;
end process;
end architecture;