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That's the code:

module flipflop (input logic clk, reset, 
                 input logic [7:0] qin, 
                 output logic [7:0] qout);
timeunit 1ns;

always @(posedge clk or posedge reset)
  if (reset)
    qout = '0;
  else
    qout = qin;

endmodule 

testbench:

module testflop ();
timeunit 1ns;
timeprecision 100ps;
   

logic reset;
logic [7:0] qin,qout;

// ---- clock generator code begin------
`define PERIOD 10
logic clk = 1'b1;

always
    #(`PERIOD/2)clk = ~clk;

// ---- clock generator code end------


flipflop DUV(.*);
default clocking cb @(posedge clk);
default input #1step  output #4;
  input qout; 
  output reset, qin;
endclocking

  initial
   begin
    cb.qin <= '0;
    cb.reset <= 0;
    ##2 cb.reset <= 1;
    ##3 cb.reset <= 0;
    for (int i = 1; i < 8; i++)
      begin
         ##1 cb.qin <= i;
      end 
     ##3;
     $finish();
    end
endmodule     

And this is the waveform:

I can see the #4ns skew for outputs, but I cannot see the #1step skew for the input.

What's wrong?

Is the #1step supposed to be equal to the timeprecision?

enter image description here

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1 Answer 1

6
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There is nothing wrong; the simulation behaves as expected. The clocking block applies the 4ns delay to the output as expected and as seen in your waves.

However, the clocking block does not apply any delay to the input. The clocking block samples the input before the rising clock edge. Refer to IEEE Std 1800-2017, section 14.4 Input and output skews:

Input (or inout) signals are sampled at the designated clock event. If an input skew is specified, then the signal is sampled at skew time units before the clock event. Similarly, output (or inout) signals are driven skew simulation time units after the corresponding clock event.

Since you specified 1step, the input is sampled 100ps before the rising edge of the clock. One step is equal to the timeprecision. The sampling point will not be visible in the waveforms since it is not a separate signal.

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