I want to design a brand new PCB board for Altera Cyclone III FPGA with 144 IO pins, such as ep3c25e144. However, I am clueless of how the process can be done in Eagle Cadsoft.
Even when they provide one package for EQFP144,I still don't know how to map the pin. Also, as far as I know, we also need to map 8 IO Banks of the FPGA.
Can someone please provide some guidance?
FPGA design is usually a bit more complex given that there are so many options available, depending on what you want to accomplish. Here are some of the main things to look at:
1) Determine the bank allocation as far as voltages and anything else that might be needed for your board. Altera Quartus II is good for giving you a pin layout (look at pin planner tool) so you know what the capabilities of each pin are and so you can decide the voltage and use of each pin.
2) You can use the altera tools to get an idea of current draw. Note that FPGAs are notorious power hogs (especially at startup peak and with many I/Os driven) and you need to be quite conservative in this sense.
3) Find a reference design for the 3C25 part. Altera has several reference boards and schematics. Scrutinize them for their recommendation of power regulation parts to ensure proper power. Same for clocks.
4) Find or create the Eagle footprint. Altera has some guidelines I believe, though it is better to obtain something already made. Since the part you need is QFP, it's not as bad as BGA. Make sure to look for footprints that might be for other parts but are equivalent (pin, pitch, other specs should be the same).
5) Create or find footprints for other parts and finalize the schematic.
6) PCB layout is usually critical for high speed, and BGAs can be difficult to fan out (especially since eagle isn't much help here). QFP not so much. Read the Altera app notes (and look at the reference design PCBs) to place the capacitors as close as possible for proper decoupling. This is critical.
First understand the chip's general pinout requirements due to fixed pin functions, I/Os with limited physical alternatives, and banked resources.
Understand the limitations of the total number and physical location options of specific resources like power supply pins, ground pins, clocks, transceivers, configuration pins, et.al.
Understand your design at the implementation level and how its I/Os and clocks can optimally map according to I/O protocol, I/O voltage, routing to nearby LUTs, sharing clocks, et. al. Ideally you'll fix few arbitrarily selectable I/Os for particular design signal usages until you've completed the synthesis, implementation, and simulation / testing of your design. Constraining given internal signals to given external I/Os just limits the efficiency of the implementation and routing of your design, so let the synthesis and implementation tools proceed with relatively few constraints dictated by arbitrary I/O assignments.
Once you have a proposed pinout then check how well it might work considering timing and other analyses, PCB layout / routing concerns, et. al. Pin swap / rearrange as needed to optimize the pinout appropriately balancing PCB concerns and FPGA routing / timing / resource concerns.
Then lock your design to the chosen I/Os and design the schematic and layout accordingly.
http://www.altera.com/education/univ/materials/unv-overview.html
http://www.altera.com/education/univ/software/quartus2/unv-quartus2.html
http://www.altera.com/support/design-support-resources/spt-index-guide.html
http://www.altera.com/products/software/flows/fpga/flo-fpga.html#fpga
