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This NAND gate in the 6502, T2 and T3 are really easy to understand, they do A∧B. The output is before T2 and T3, to invert it. The T1 transistor is default-on. Why is it there?

enter image description here

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T1 functions as a pull-up resistor for T2 and T3.

Like most early MOS microprocessors, the 6502 used NMOS process technology, a simpler, lower-cost type, compared to CMOS which is the dominant process technology today.

In this NMOS gate, T1 is a depletion-mode device connected as a pull-up. As you noted, being depletion-mode, with the gate connected to source it is biased 'on'. But T1 has another difference from T2 and T3: it is sized to have a higher drain-source resistance, by using a longer and thinner source-drain channel. As such, T1 stays on all the time and behaves like a resistor.

More about NMOS pull-up sizing here: https://www.idc-online.com/technical_references/pdfs/electronic_engineering/An_Nmos_Inverter.pdf

T1's source and gate will be pulled down when T2 and T3 are both turned on, and pulled up if either T2 or T3 are off. This implements the NAND function Y = !(A & B). Simulate it here

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In contrast, the CMOS version of NAND uses four enhancement-mode, low resistance FETs: two p-FETs in parallel for the pull-up, and two n-FETs in series for the pull-down. That looks like this (simulate it here):

enter image description here

More about CMOS here: https://www.elprocus.com/cmos-working-principle-and-applications/

The CMOS gate has two advantages over NMOS:

  • CMOS uses no current in either state; NMOS use current when making a 'low' output
  • CMOS uses a low-resistance p-FET to drive the output high for low rise-time; NMOS relies on the depletion-mode pull-up, which is slower

These CMOS advantages are why you rarely see NMOS used today, despite the higher cost of CMOS process. As it is, many of the early NMOS processors eventually moved over to CMOS, including the 6502 (as the 65C02.)

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  • \$\begingroup\$ I like this answer. +1. I've a question, though. My recollection is that all of the NMOS MCU devices I used required the external generation of two clocks in anti-phase. They were a pain to clock and MCU manufacturers would sometimes offer a separate IC to help generate the clocks [and some other bus control support.] I never did see an NMOS MCU without having to provide a 2-phase non-overlapping clock to the darned thing. (Includes the NMOS 6502, memory serving.) But when CMOS arrived, single clocks were fine. What's the reason for that? Is it related to NMOS itself? \$\endgroup\$
    – jonk
    Sep 15 at 1:01
  • \$\begingroup\$ Two-stage pipe? \$\endgroup\$ Sep 15 at 1:06
  • \$\begingroup\$ I'm pretty sure it was not related to that question. The reason is that as soon as CMOS became available the NMOS processes (some of them, anyway) were converted over. And in every case I experienced (NMOS 8080 --> CMOS 8080; NMOS 6502 --> CMOS 6502, etc.) the newer design left the old clocking behind. This was an over-night change and I believe the re-designs were minimal -- they wanted the advantages of CMOS. But it appeared that part of what came with CMOS was a single clock. I'm almost sure it was about the process change. But I don't recall why, anymore. Maybe it will come back to me. :) \$\endgroup\$
    – jonk
    Sep 15 at 2:05
  • \$\begingroup\$ Oh... Just a tickle in the back of my mind flooded back.... The CMOS could be clocked all the way down to zero. The NMOS could NOT be!! It didn't retain its register values below some minimal clock rate -- so frequent refreshing was required. But with CMOS, it wasn't. I suspect the clocking was required because of the way that the register memory was maintained in NMOS. I'll dig around. I've forgotten so much. \$\endgroup\$
    – jonk
    Sep 15 at 2:08
  • \$\begingroup\$ I think I found it!!! Page 310 and 311 of "Designing Sequential Logic Circuits", 2002, by Jan Rabaey. At least, a significant part of it, anyway. By the way, that book also confirms what you write about the power consumption of NMOS and the advantage of CMOS, here. This is the primary reason there was such a shuffle to get to CMOS from NMOS for CPUs. NMOS was literally burning up and they needed something to get the power lower. CMOS was the answer to this significant problem, according to the book. \$\endgroup\$
    – jonk
    Sep 15 at 2:28

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