This NAND gate in the 6502, T2 and T3 are really easy to understand, they do A∧B. The output is before T2 and T3, to invert it. The T1 transistor is default-on. Why is it there?
T1 functions as a pull-up resistor for T2 and T3.
Like most early MOS microprocessors, the 6502 used NMOS process technology, a simpler, lower-cost type, compared to CMOS which is the dominant process technology today.
In this NMOS gate, T1 is a depletion-mode device connected as a pull-up. As you noted, being depletion-mode, with the gate connected to source it is biased 'on'. But T1 has another difference from T2 and T3: it is sized to have a higher drain-source resistance, by using a longer and thinner source-drain channel. As such, T1 stays on all the time and behaves like a resistor.
More about NMOS pull-up sizing here: https://www.idc-online.com/technical_references/pdfs/electronic_engineering/An_Nmos_Inverter.pdf
T1's source and gate will be pulled down when T2 and T3 are both turned on, and pulled up if either T2 or T3 are off. This implements the NAND function Y = !(A & B). Simulate it here
In contrast, the CMOS version of NAND uses four enhancement-mode, low resistance FETs: two p-FETs in parallel for the pull-up, and two n-FETs in series for the pull-down. That looks like this (simulate it here):
More about CMOS here: https://www.elprocus.com/cmos-working-principle-and-applications/
The CMOS gate has two advantages over NMOS:
- CMOS uses no current in either state; NMOS use current when making a 'low' output
- CMOS uses a low-resistance p-FET to drive the output high for low rise-time; NMOS relies on the depletion-mode pull-up, which is slower
These CMOS advantages are why you rarely see NMOS used today, despite the higher cost of CMOS process. As it is, many of the early NMOS processors eventually moved over to CMOS, including the 6502 (as the 65C02.)