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I'm reading about the SPI clock polarity and phase. Specifically, this article, Figure 2. My question is about the case of CPHA = 0, CPOL = 0. For this configuration, my understanding is that the clock stays low when there is no activity, the data is sampled (read) in the leading rising edge and shifted (sent) in the falling one.

That last part is what I don't get: if the clock is low and the data is read by the receiver on the leading rising edge, that means that the receiver reads a bit before the transmitter sends anything.

What am I missing?

EDIT

I have read a verilog impl. of an SPI module and have seen that the problem I mention above is handled by not driving down the select pin until the first bit is already in MOSI. Am I right?

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  • \$\begingroup\$ Depends on slave. Some slaves put the first data on select edge. So that data is already setup before the first sclk edge for sampling. \$\endgroup\$
    – Mitu Raj
    Sep 15, 2021 at 9:38

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if the clock is low and the data is read by the receiver on the leading rising edge, that means that the receiver reads a bit before the transmitter sends anything.

Look at D7: -

SPI bus timing

(Image source: Corelis - SPI Tutorial)

It is always set up prior to reading.

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The timing diagram you linked seems pretty clear to me. The transmitter makes sure that the first bit is correct before sending the first clock pulse. The master is in control of the clock signal.

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