enter image description here

Would you place the SPDT switch in front or behind the opamp?

the benefit now is the load stays equal on the source, 49K9 Ohm .. and the opamp is jobless. but will the opamp cause noise (inverted)?

2M2 Ohm debouching or 100nF capacitors?

  • \$\begingroup\$ What are you trying to achieve with this circuit? Is this being used as a phase inverter? (That would be my guess based on the unity gain inverting buffer) \$\endgroup\$ Sep 16, 2021 at 0:03

1 Answer 1


Looks like what you're trying to do is make a +1/-1 gain switchable buffer. Your circuit needs a bit of work though.

Try this (simulate it here):

enter image description here

This gives a gain of +1 or -1, depending on the switch, and has a constant input impedance of 47 kohm to GND. If you need a different impedance change all the resistors to the same value (e.g., 49.9k).

Switch 'up' you get -1 gain (invert), switch down you get +1 (follow).

And now, a circuit that does 'soft' switching between modes (simulate it here):

enter image description here

This works a bit differently: it grounds the (+) input. It does have one drawback: the impedance changes depending on the gain setting. But it will switch modes without making much of a loud 'pop'. Since it uses a p-FET with a positive pinch-off, it could be logic controlled too with an appropriate level shifter.

Design Notes:

  • The JFET should be a type with a pinch-off between 0 and 5V (the model is set for +4V).
  • FET type could be On Semi J176-D74Z or similar (1V Vgs).
  • Input positive swing is limited by FET pinch-off to (+15V - Vgs), so +11V in the sim for a +4V pinch-off. It will soft-clip above that.
  • The recommended FET will support up to +14V max input.

And here's one that provides a consistent impedance, and uses MOSFETS instead (simulate it here):

enter image description here

This circuit can use common n-channel MOSFETS like the BSS138 or 2N7002. These are easy to find and very inexpensive. Why two? See this answer: Two directional FET switch. Is it possible?

And this fixes the impedance issue, too. When inverting, the virtual ground loads the input; when non-inverting, the (+) pull-down loads the input.

Only limitation is that the max + signal swing is (+15V - Vgs), or 13.5V for this 1.5V FET.

  • \$\begingroup\$ thnx for the anwer, what happens to the leg of the inverted input if it's not connected? ... would it make noise? as like now in your image? ... do you recommend 2M2 or 100nF parallel to the SPDT as deboucing? \$\endgroup\$ Sep 16, 2021 at 0:28
  • \$\begingroup\$ Nope, don't connect anything else. In the 'follow' config, the (-) input will be the same voltage as the (+) input due to the feedback. \$\endgroup\$ Sep 16, 2021 at 0:31
  • \$\begingroup\$ so, no debouching caps? ... to prevent switching noise. looks good in the simulator, glad that i asked. it saves me 1 resistor. \$\endgroup\$ Sep 16, 2021 at 0:34
  • \$\begingroup\$ The op-amp will return to ground while the switch makes its swing. It could 'pop' when it reconnects, depending on the phase of the signal. There isn't a way to fix this with caps, you'll need to design some kind of muting circuit or use a soft switch technique. \$\endgroup\$ Sep 16, 2021 at 0:42
  • \$\begingroup\$ well, i could add a capacitor after the opamp to prevent the pop damaging the opamps after that. \$\endgroup\$ Sep 16, 2021 at 0:53

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