# How to overclock STM32F303VC and make it work at 72MHz?

I am trying to overclock my STM32F303VC. Unfortunately I can't due to a HARD FAULT EXCEPTION. Could you help me to find the error?

I also attached the code.


RCC->CR|=1<<16;
while(((RCC->CR)&(1<<17))!=(1<<17));//HSEON

RCC->CFGR|=(1<<18)|(1<<19)|(1<<20);//PLLMUL

RCC->CFGR|=(1<<13);//PPRE2
RCC->CFGR|=(1<<10);//PPRE1
RCC->CFGR|=(1<<8);//PPRE1

RCC->CFGR|=(1<<16);//PLLSRC

RCC->CR|=(1<<24);
while(((RCC->CR)&(1<<25))!=(1<<25));//PLLON

RCC->CFGR|=(1<<1);//SWS E SW

while(((RCC->CFGR)&(1<<3))!=(1<<3));



• It is usually better to post code as text rather than as a picture.
– JRE
Sep 16 at 17:41
• It's not called overclocking if you are trying to use a part that is rated to work at 72 MHz at a rate of 72 MHz. Please let CubeMX or CubeIDE to generate a working clock init for you. There is no need to put energy into re-inventing the wheel, when you could just write your application code. Sep 16 at 17:57
• Again, use CubeMX to generate the code. Copy as required. It will work you through the settings. Sep 16 at 18:39
• Save your sanity (and ours) by using the bit-mask definitions when you configure the registers. A line of code like RCC->CFGR |= RCC_CFGR_PPRE2_DIV1 is far easier on the eyes than RCC->CFGR|=(1<<13) for example. Sep 16 at 21:08
• And in addition to the above, what's conspicuously absent from your code snippet is something to configure the Flash Latency. If you want to run the HCLK at 72MHz you have to configure the Flash for a latency of 2 wait states (FLASH_ACR register, ref manual page 78) before raising the bus clock. Overclocking the Flash is almost guaranteed to cause HardFaults because it'll be giving the core invalid instruction code to execute. Sep 16 at 21:11