I need it for equivalent time sampling. This will be the signal for ADC clock, I will use a Schmitttrigger to make it "digital"
Unless you have other special needs, like having to precisely align the ADC sampling aperture, it could be simpler to use an oversampling ADC at a few hundred kHz Fs, and resample to 19.99995 kHz in the digital domain.
Besides that, you could use an audio DAC which already includes the oversampling filter and alias-reject output filter, so you don't need to implement it.
Get a 24.576MHz canned oscillator, use that as master clock for the DAC and also feed this clock to the FPGA. In the FPGA, divide it down to get your 192ksps sampling frequency, run the DDS on that sampling rate, and output your 19.99999 kHz sine wave over an I2S port. I2S is very simple to do in a FPGA.
You will get a very clean sine wave at the frequency you want without having to implement any complicated filters.
If you don't want to use an audio DAC chip, then since you need the highest possible sampling frequency to simplify the output filter, you could use a sigma delta DAC core in the FPGA, and an external RC lowpass filter. Since it's a 1-bit DAC, it needs to operate at the highest possible frequency. Fortunately, it's quite a simple digital circuit, so modern FPGAs should have no problems running it at a very fast clock.
However, since the goal is to generate a square wave clock and not a sine wave, you could simply use a Fractional-N PLL chip instead of DDS.