# Generating high frequency resolution sine wave

I want to generate a sine wave with a frequency of exactly 19.999995 kHz. This is possible with a DDS generator implemented inside a FPGA. The DDS signal will be a digital one. So I will use a DAC to make it analog. A DAC with a sampling rate of 40kHz (nyquist theorem) should be enough to generate a sine wave with excatly this frequency?

I will place a lowpass afterwards.

Is this filter a good choice?:

• That's a difference of 5 parts per million. what is the use case for this? I ask because there are many footguns you can aim at yourself when trying to generate very finely grained frequencies, and maybe we can save you a lot of work and frustration by pointing you in the right direction from the start. Commented Sep 16, 2021 at 18:06
• your oscillator accuracy will likely be worse than 250ppb, so the actual frequency will drift around 20 kHz anyway Commented Sep 16, 2021 at 18:24
• Yes, that is exactly right, as far as "this frequency" goes, as long as you have exactly 19.999995 kHz at whatever shape it is. DAC may be used, too. You build high Q filter, that almost goes into oscillation at 19.999995kHz (or just close to it), then Nyquist can regenerate a sine wave. However, at Nyquest rate, your DAC will be generating square wave, give it about 8x to 16x faster speed, then you would feel much happier with the output.
– jay
Commented Sep 16, 2021 at 18:26
• so, couple of problems! let's assume you have a perfect 8 bit DAC, and a perfect clock source for your DDS. At these 8 bit resolutions, the first couple thousand oscillations look exactly the same for 20 kHz and (20 - 5e-6) kHz. Nothing you can do about this – other than having a very sharp low-pass filter which will actually have an impulse response long enough to allow for that. So, your "good" reconstruction filter actually will have to have a time constant in the order of 1000 s or more. You'll have to wait multiple of these for an analog system to stabilize. Commented Sep 16, 2021 at 18:27
• More bits make discrete periods look slightly different earlier. OK. Higher DAC sampling rate also has that effect. But you're still trying to feed something with harmonics into a schmitt trigger (are you sure you want a Schmitt trigger for this?), not even mentioning other noise sources, so your harmonic suppression will need to be much better than the differences in values - building an analog filter with >> 60 dB suppression is non-trivial. Commented Sep 16, 2021 at 18:30

Most likely you would be unhappy with the results.

You would need extremely steep brick wall filter to pass 19.999995 kHz but block 20.000000 kHz, it will be extremely impractical to realize that with physical components. At least you would need to remove the image that happens at 20.000005 kHz.

Your required output frequency is extremely close to half of the sampling rate, so expect a lot of DAC aperture loss.

As a rule of thumb the usable output frequencies are sometimes estimated to be about 80% of Nyquist frequency.

• so I could use a sampling frequency of lets say 100kHz. And a bandpass with a high Q of around 100 wouldn't be enough to just pass the 19.999995khz and block everything else? Commented Sep 16, 2021 at 18:01
• you don't need a bandpass, you need a low pass that let's through your frequency of desire and removes (f_sample - freq_of_desire) and anything above. Note that it takes a relatively long term until you can see the difference between a 20kHz - 5·10⁻⁶ kHz and 20 kHz, when you have a DAC that is of finite resolution. Commented Sep 16, 2021 at 18:03
• @MarcusMüller ok thanks. If fsample = 100kHz. A good lowpass fc = 25khz should be enough to give me my desired frequency output right? Commented Sep 16, 2021 at 18:09
• don't think you realize how good "good" needs to be! Commented Sep 16, 2021 at 18:22
• To the OP: Rolloff for an RC is 20 dB per decade (10 x freqency) or 6 dB per octave (2x frequency). Between 25 kHz and 100 Hz, you have two decades (25 kHz x2 = 50 kHz, then 50 kHz x2 = 100 kHz). So that is 12 dB for a simple RC low-pass. If you use two RC's you can get 24 dB. Etc. I am guessing you don't know how much attenuation you need. Do you need 40 dB or 60, 80 120 dB? So all I can say is that you should run the DAC as fast as you reasonably can. I would not go less than 10 MHz. This will allow you to very effectively filter the sampling frequency. Commented Sep 17, 2021 at 6:18

You will get the exact divided frequency from a DDS, but it will aliased with the sampling frequency.

Frequency output

The typical output spectrum of the DDS RF signal generator set to 35MHz is shown on the following picture (spectrum analyzer set to 50MHz/div horizontal resolution and 10dB/div vertical resolution):

The highest peak on the left is the DC component, followed by the fundamental DDS signal at 35MHz.

Programmed output frequency is 35MHz. You get: 35MHz, 165MHz, 235MHz, 365MHz, 435MHz, 565MHz, 635MHz, 765MHz, 835MHz or 965MHz at a nominal DDS clock frequency of 200MHz.

You do need a filter to eliminate those aliases.

It will be much better to run the DAC much faster. Then the filter will be easier to design and build.

For example, if the sampling frequency is 10 MHz, then the low pass could be set at 100 KHz. You could cascade two passive RC stages followed by an op-amp buffer.

With two decades of decades frequency between cutoff and sample frequency, and 40 dB per decade rolloff, you could get 80 dB of attenuation at the sample frequency. Maybe that would be enough.

The closer the DAC frequency is to the frequency of interest, the more difficult the filter design will be. And there is no reason for it, because running a DDS at 10 MHz is no problem.

I need it for equivalent time sampling. This will be the signal for ADC clock, I will use a Schmitttrigger to make it "digital"

Unless you have other special needs, like having to precisely align the ADC sampling aperture, it could be simpler to use an oversampling ADC at a few hundred kHz Fs, and resample to 19.99995 kHz in the digital domain.

Besides that, you could use an audio DAC which already includes the oversampling filter and alias-reject output filter, so you don't need to implement it.

Get a 24.576MHz canned oscillator, use that as master clock for the DAC and also feed this clock to the FPGA. In the FPGA, divide it down to get your 192ksps sampling frequency, run the DDS on that sampling rate, and output your 19.99999 kHz sine wave over an I2S port. I2S is very simple to do in a FPGA.

You will get a very clean sine wave at the frequency you want without having to implement any complicated filters.

If you don't want to use an audio DAC chip, then since you need the highest possible sampling frequency to simplify the output filter, you could use a sigma delta DAC core in the FPGA, and an external RC lowpass filter. Since it's a 1-bit DAC, it needs to operate at the highest possible frequency. Fortunately, it's quite a simple digital circuit, so modern FPGAs should have no problems running it at a very fast clock.

However, since the goal is to generate a square wave clock and not a sine wave, you could simply use a Fractional-N PLL chip instead of DDS.

When it is about high resolution and Sine synthesis there are maybe three important rules:

1. put your sampling frequency as high as feasible to reduce the artifacts illustrated by @MarkoBuršič . That way you will have plenty of bandwith for your lowpass to work on.

Now (1) will make it easy to reject the sampling frequency artifacts in your output. But anyway the synthesized frequency will generate harmonics which are inevitably very close (at 2x19.999995 kHz, 3x19.999995 kHz, ..). So there are more means necessary to reject those:

1. Use dithering along with your DDS to prevent all the harmonics of your synthesized frequency, especially if you use a low precision DAC like 12-bit or 8-bit. For multibit DACs, use +/- 1 LSB triangular distributed dither, to fully reject all harmonics caused by the limited digital precision of the DAC

2. Any multibit DAC will have integral nonlinearity (INL) which again causes harmonics to appear to due its analog performance. To minimize this, use a 1-bit DAC, with very high sample rate. You can directly use the FPGA output for this, but might want to remove the jitter with an external flipflop.

As your 19.999995kHz signal will alias to 20.000005 kHz (sampled at 40kHz) you will see the sum of both these signals, which will beat with each other at 0.01Hz.

So, every 100 seconds they will cancel out and your signal will disappear.

As others have said, you need a higher sampling frequency. That way the alias frequency will be far enough from the frequency of interest that you can design a filter to accept one and reject the other.