I configured my FPGA (Artix-7, -1 speed grade) to run a clock at higher speeds than it is designed for (464MHz). Naturally, I received the below egregious timing errors when implementing a 12-bit counter but I went ahead and generated a square wave using the counter to see if the clock could run at such a speed (I was interested in making a faster PWM DAC).

The oscilloscope confirmed the clock was indeed running at 800MHz and the square wave appears normal. Why aren't the timing issues causing glitches in the square wave? Everything is failing setup requirements...

enter image description here

enter image description here

From the oscilloscope:

$$\text{square wave frequency} = \frac{1}{5.14\text{us}} = 194.5\text{kHz}$$ $$\text{clock frequency} = \text{square wave frequency} \cdot 12\text{-bits} = 194.5\text{kHz} \cdot 4096 = 796\text{MHz}$$

  • \$\begingroup\$ That's not how timing analysis works. Read about 'PVT corners in VLSI design'. \$\endgroup\$
    – Mitu Raj
    Commented Sep 17, 2021 at 4:36
  • \$\begingroup\$ "The oscilloscope confirmed the clock was indeed running at 800MHz and the square wave appears normal. "- it doesn't look normal to me. Seems to be some really bad jitter. \$\endgroup\$ Commented Sep 17, 2021 at 6:25
  • \$\begingroup\$ Is this square wave properly in sync with all the other square waves you didn't measure? \$\endgroup\$ Commented Sep 17, 2021 at 16:52
  • \$\begingroup\$ @user253751 actually yes. Because if you run this through a low pass filter then you get a DC output and my DC output did not fluctuate as you would expect if there were deviations in duty cycle. The DC output from the Low pass filter is showing millions of square waves in a few seconds and the output was quite clean which is why I’m so confused about this. Correct me if I’m wrong about that proving the stability/integrity of the square wave \$\endgroup\$
    – Andrew
    Commented Sep 17, 2021 at 20:30
  • \$\begingroup\$ @Bruce Abbot if jitter is a deviation in the true periodicity then I’m not sure how you see that from the picture. See my answer above regarding the periodicity. I think you are referring to the edges of the square wave where it looks like a secondary voltage level continues past the larger edge? \$\endgroup\$
    – Andrew
    Commented Sep 17, 2021 at 20:37

2 Answers 2


Now go build 10,000 of your circuit, and test them at the FPGA's maximum rated ambient temperature and lowest specified power supply voltage. Do they all work?

The timing analysis isn't telling you that the design will fail on your particular sample of the FPGA operating at room temperature and nominal supply voltage. It's meant to tell you (if it passes) that the design will work on all samples of the FPGA at all temperatures and supply voltages that are allowed by the datasheet. By nature it must be somewhat conservative.

  • \$\begingroup\$ Are you saying that this design may work 99% of the time at "normal" environmental conditions? Did I get "lucky"? How do I know when the constraint's failure will cause an actual failure? How do I know how close I am to failure? I might understand what you're saying if I was running at 500MHz but I've gotten this to run at twice the rated frequency before with no glitches (900MHz). \$\endgroup\$
    – Andrew
    Commented Sep 17, 2021 at 2:40
  • \$\begingroup\$ "How do I know how close I am to failure." If you can't close timing, then you are too close to failure. In order to ignore a failure to close timing, you have to be more experienced and knowledgeable than the people who designed the compiler and synthesis tools and timing analyzers. Because they are the ones who are telling you that the timing will not close. \$\endgroup\$
    – user57037
    Commented Sep 17, 2021 at 6:58

enter image description here

Normally your analog clock ought to have jitter noise maybe 0.1% of the sine Vpp or SNR = 60 dB but clipped to logic levels, which translates to maybe 1 error in your lifetime from random noise. Measuring real SNR is hard to do unless you have the tools and access to the eye pattern with worst-case stress levels (Schmoo plot)

But your results are far from that.

For commercial products you want to perform a PVT or worse case process, voltage and temperature variance test to determine margin to failure. Then have a 6 sigma yield.

It would perform much worse with heat and -10% voltage and better with +10%V as long as that did not raise the temperature significantly, which is possible. For these frequencies, you need to use CML (current mode logic) and not VML (voltage mode ... the normal stuff) or maybe GaAs or SiC prescalers.

But this is hypothetical since all you want is to raise the PWM much higher f which is easily done with dedicated PWM chips.


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