I'm studying pass transistors. One thing I came across in several of the books is that when an NMOS has a logic state HIGH and the input terminal (the schematic below) is also HIGH, the output terminal will be HIGH (a weak HIGH to be more specific) as well. Most of the books draw the output terminal open (and nothing attached to it) so for the NMOS device to be on initially it had seen the "Output" named terminal being in a lower potential but actually the terminal is open, not connected ground or anything. So,

What is actually happening here? How can the NMOS device consider the open terminal it 0 volts initially and consider it as the source terminal and Vgs > Vth so channel forms and we get a weak HIGH at the output?

(I know that there's parasitic capacitances at each terminal of a MOS device. Is it because the parasitic capacitance has initially 0 charge? Maybe that's why it's happening?) enter image description here

Previous picture before edit :


simulate this circuit – Schematic created using CircuitLab

  • \$\begingroup\$ Check if the IRF530 has an internal diode connected between the source and drain. It's usually a characteristic of the MOSFET construction. \$\endgroup\$
    – Transistor
    Sep 18, 2021 at 18:29
  • \$\begingroup\$ Yes, actually it does. I guess I shouldn't have used simulation here. I'm mainly asking the theoretical perspective here. Can a open terminal in this case the "output" node be considered to be in a lower voltage? if so then why? \$\endgroup\$ Sep 18, 2021 at 18:47
  • \$\begingroup\$ I have edited the picture so that you can understand better. Thanks. @Transistor \$\endgroup\$ Sep 18, 2021 at 18:53
  • \$\begingroup\$ Sorry for the bad edit. I've corrected it. \$\endgroup\$ Sep 18, 2021 at 19:12
  • \$\begingroup\$ the diode (actually the bulk-drain junction) is connected to the source in most discrete MOSFETs you buy (these are LDMOS, power transistors). In an integrated circuit, there are more options, and generally in logic, the bulk of all MOSFETs is connected to ground -- not the source of the individual transistor. \$\endgroup\$
    – jp314
    Sep 18, 2021 at 19:47

2 Answers 2


In MOS circuits, it doesn't really make sense to analyze an open output like that -- when the gate V is 0, the voltage at the output will be somewhat indeterminate and will generally drift (slowly) towards 0. Usually there are some other complimentary signals that will drive that high impedance node in that condition.

In your circuit, the NMOS with VG=3 and VS=3 (and bulk generally =0), will act as a source follower (source and drain are interchangeable) -- the output will follow a threshold voltage below the input. So say VTH = 0.7, then the output will be pulled up to about 3-0.7 = 2.3 V. This is not a full rail signal, but may be sufficiently high be considered a logic '1' by following logic.

So, you do get a weak high.


enter image description here

Figure 1. Source: Vishay datasheet.

Note the diode between source and drain. This is a result of the construction process and can be quite useful in some designs.

  • \$\begingroup\$ Thanks for your response. But as I've mentioned I'm not particularly asking about the transistor model or structure. I've changed the picture to something that provides more context to the question. Thanks \$\endgroup\$ Sep 18, 2021 at 18:55

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