# How to read "inverted" uart signal

I have am experimenting with an MDB device. I have a simple setup, with an MDB master, and my own NXP EVK board which acts as slave.

I started with just a logic analyzer, to verify that I see communication on the bus. In the image below I can see the master is polling.

I had to change some settings in the channel analyzer in order to read this.

I need to "invert" the signal. I don't fully understand what that means. I thought it would mean that 1s are 0s and vice versa. Reading this answer made clear it's more complicated than simply inverting all bits. (still have a hard time really understanding what it is).

Anyway, I thought let's try to read this in my NXP chip. So I hooked up the master signal to my LPUART3 rx pin, enabled interrupts and read the DATA register when the interrupt fires.

In my main function I print the 16bit word in both hex and binary to see what I receive.

I am looking at the bits of 0x13b vs 0x112 (for probably way too long now) and trying to see the magical trick how to convert it. I don't see it. At all.

Who can make me a bit smarter on this topic?

• Just to be sure, have you connected the logic analyzer probe to a TTL/CMOS voltage level output that for some weird reason os inverted, or, to an RS232 voltage level output that by definition inverts the signal but also uses higher voltages that are not TTL/CMOS compatible? Sep 18, 2021 at 22:03

I need to "invert" the signal. I don't fully understand what that means.

It means you have put the signal through an inverter before sending it to the UART RX input, so that high becomes low and low becomes high.

I thought it would mean that 1s are 0s and vice versa.

Yes, but the 'idle' level between frames also needs to be inverted, so the UART can tell where the framing (Start and Stop) bits are. Without this the idle state will be seen as Break, then the start bit is seen as Idle, the first '0' bit is seen as the Start bit etc. Inverting the received data coming out of the UART won't help because it has been irreversibly mangled (perhaps missing bits, or starting part way into the frame and picking up bits from the next one).

Your result of 0x13b vs 0x112 is entirely consistent with a signal that is 'upside down'. Switching 100111011 around to go from lowest to highest bit gets 110111001. Before this is the low 'Start' bit (second '.' in your trace), followed by two '1's, a '0', 3 more '1's, 2 more '0's (last '.' plus the actual Stop bit) and finally a high 'Stop' bit which is actually the next Start bit.

Standard UART serial interface is using logic H (1) also known as "mark" as the idle signal level and then the transaction on the line starts with a "start bit" that is encoded as a "L" (or 0) for the duration of one bit period. The data bits then follow and the last bit is the Stop bit coded as "H" (1).

The chart you provided suggests that your signal is inverted - the base level (when nothing happens) is L instead of H.

Placing an invertor in-line will change tje signal to what normal TTL level UART receiver expects.

History lesson: The reason for idle level being H is to detect that the signalling circuit is intact. The UART (asynchronous receiver) technology has its roots in teletype communication. There two machines were connected over a distance through a pair of wires in a loop that was connected to a current source (battery and resistor). The nominal (20mA) current was present all the time. When the transmitter was sending a character it first interrupted the current loop for the duration of one bit interval to start the decoder at the remote end. Then the series of bits were transmitted as closed loop (current present = 1) or open loop ( =0) during each of the bit intervals. Typical Baudot (Bd) rate used for teletype was 50Bd and the symbols were encoded in only 5 bits.