VHDL near text "begin"; expecting "end" Error

Question

I'm trying to learn VHDL and and trying to create an 8 bit 4 to 1 MUX. Below is my code:

LIBRARY ieee;
USE     ieee.std_logic_1164.all;

PACKAGE inputarray_type IS
TYPE inputarray IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
END PACKAGE inputarray_type;

USE work.inputarray_type.all;

ENTITY bit8mux4to1 IS
    PORT (inputs    :   IN inputarray;--ARRAY (3 DOWNTO 0) of STD_LOGIC_VECTOR (7 DOWNTO 0); 
    s   :   IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
    output          :   OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bit8mux4to1;

ARCHITECTURE structure OF bit8mux4to1 IS 
    COMPONENT mux4to1
        PORT(i0, input1, i2, i3, s0, s1 : IN    STD_LOGIC;
        output  :   OUT STD_LOGIC);
BEGIN
    generate_mux: FOR i IN 0 TO 7 GENERATE
        stage0: mux4to1 PORT MAP (inputs(0)(i), inputs(1)(i), inputs(2)(i), inputs(3)(i), s(0), s(1), output(i));
    END GENERATE generate_mux; 
END structure ;

The component mux4to1 works, and I've used it as a component in other code.

When I try to compile the code I get an error saying

"VHDL syntax error at bit8mux4to1.vhd(21) near text "BEGIN"; expecting "end"

I've tried changing the generate statement many ways and have tried commenting every line of the generate statement completely, but the error won't go away. What is the problem? Is there something wrong with the architecture?

Answer 1

There are two errors:

1. The lack of an END COMPONENT stanza
2. VHDL only allows one object per file; if you want more than one object in the same file, you need to repeat the LIBRARY stanza, it behaves as a completely new logical file.

Corrected code (verified with Synplify Pro):

LIBRARY ieee;
USE     ieee.std_logic_1164.all;

PACKAGE inputarray_type IS
TYPE inputarray IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
END PACKAGE inputarray_type;

-- Different logical file below

LIBRARY ieee;
USE     ieee.std_logic_1164.all;
USE     work.inputarray_type.all;

ENTITY bit8mux4to1 IS
    PORT (inputs    :   IN inputarray;--ARRAY (3 DOWNTO 0) of STD_LOGIC_VECTOR (7 DOWNTO 0); 
    s   :   IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
    output          :   OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bit8mux4to1;

ARCHITECTURE structure OF bit8mux4to1 IS 
    COMPONENT mux4to1
        PORT(i0, input1, i2, i3, s0, s1 : IN    STD_LOGIC;
        output  :   OUT STD_LOGIC);
    END COMPONENT;
BEGIN
    generate_mux: FOR i IN 0 TO 7 GENERATE
        stage0: mux4to1 PORT MAP (inputs(0)(i), inputs(1)(i), inputs(2)(i), inputs(3)(i), s(0), s(1), output(i));
    END GENERATE generate_mux; 
END structure ;