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I'm building a 6502 (WDC 65C02S) computer, for now on a breadboard (maybe later will I hopefully learn and move to a PCB). In my Address Decoding Logic I'm using several NAND and 4-input NAND gates (74HC00 and 74HC20).

The maximum I have is a chain of 4 74HC gates between some address lines and the IC they control. VOltage is 5V.

My question is about what timing information is the relevant one (in the 74HCxx datasheets) to figure out the maximun frequency I could run the design at before I likely run into troubles.

My question is only about the 74HC cascading timing constraints. I know the breadboard is far from ideal, and of course I might have other ICs on the board with other limits/rates, but I'm interested on what I should focus at in the 74HC00/20 datasheets).

Right now my guess is:

At 4,5V max propagation delay is 18ns. 4x18ns is 72ns.

If I run at 2MHz, it's a 500ns period. 500 ns >> 72 ns so I should be fine. Is my thinking correct?

If I were to push it to 12MHz, period would be 83ns, which is above but close to the 72ns of 4 74HC cascading gates. My guess is 12MHz would be the limit I could go up to.

Am I right, or is my reasoning flawed? Thanks in advance for your help to understand this.

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    \$\begingroup\$ You seem only to be considering address decoding time, which is important but far from the only thing going on. There’s a lot more that needs to happen each bus cycle. Have you considered access times of RAM, ROM, I/O devices, setup and hold times for data on the data bus? Have you looked at the bus cycle timing of the 65C02? \$\endgroup\$
    – StarCat
    Sep 19, 2021 at 18:04
  • \$\begingroup\$ You're right, I know there are other thing to consider. Hence I especially said I only consider this in my question, for the purpose of keeping the question on its point. I don't think I'm going to find these other considerations in the 74HCxx datasheet am I 😉 \$\endgroup\$
    – Alexandre Dumont
    Sep 19, 2021 at 18:32
  • \$\begingroup\$ Use ACT series. Decoders are a little slower than gates, but likely shorter than 4 stage gate delay. If you do not need to cover complete address space, you do not need to decode all but use address bits as CS. \$\endgroup\$
    – jay
    Sep 19, 2021 at 20:26
  • \$\begingroup\$ As Starcat mentions, the decoder delay is only part of a system. Trying to relate clock speed of the cpu to decoder prop delay is useless. Based on your 12MHz example, the decode prop delay might be perfectly acceptable if you had a 5ns ram chip, the cpu with a 5ns setup time and 1ns of bus delay. \$\endgroup\$
    – Kartman
    Sep 19, 2021 at 23:42

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Short answer: It depends.

Long answer: The propagation time through your combinatorial logic isn't the only factor to consider. You mention that you are using it for address decoding. What is the input setup time on the peripheral chip you are talking to? What is the 6502's input setup time on a READ transaction? What is the 6502's "address valid after cycle start" time?

Your min cycle time (max operating frequency) is the sum of the max values for 6502 address valid, address decoding (your NAND devices), peripheral address setup time, peripheral output delay, and the 6502 input setup time. There is also PWB trace delay, but those are likely negligible at these lower frequencies.

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