I'm building a 6502 (WDC 65C02S) computer, for now on a breadboard (maybe later will I hopefully learn and move to a PCB). In my Address Decoding Logic I'm using several NAND and 4-input NAND gates (74HC00 and 74HC20).
The maximum I have is a chain of 4 74HC gates between some address lines and the IC they control. VOltage is 5V.
My question is about what timing information is the relevant one (in the 74HCxx datasheets) to figure out the maximun frequency I could run the design at before I likely run into troubles.
My question is only about the 74HC cascading timing constraints. I know the breadboard is far from ideal, and of course I might have other ICs on the board with other limits/rates, but I'm interested on what I should focus at in the 74HC00/20 datasheets).
Right now my guess is:
At 4,5V max propagation delay is 18ns. 4x18ns is 72ns.
If I run at 2MHz, it's a 500ns period. 500 ns >> 72 ns so I should be fine. Is my thinking correct?
If I were to push it to 12MHz, period would be 83ns, which is above but close to the 72ns of 4 74HC cascading gates. My guess is 12MHz would be the limit I could go up to.
Am I right, or is my reasoning flawed? Thanks in advance for your help to understand this.