I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board. My design is using one PLL that I added a while ago in Platform Designer. Though it isn't explicitly calling Fractional PLL based on the input/output ratio (50MHz/32.768MHz) it is almost certain that this IP must be fPLL.

Now I added another PLL instance to generate 7.68MHz clock and I am getting an error from Quartus Fitter:

    Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
    Error (175001): The Fitter cannot place 1 fractional PLL, which is within PLL Intel FPGA IP soc_system_pll_0.
        Info (14596): Information about the failing component(s):
            Info (175028): The fractional PLL name(s): soc_system:u0|soc_system_pll_0:pll_0|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
        Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
            Error (11239): Location FRACTIONALPLL_X0_Y1_N0 is already occupied by soc_system:u0|soc_system_pll_1:pll_1|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL.
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

I am confused since Quartus reports that only 2/5 PLLs available on the silicon are utilized. (And that makes sense since previously the design was using 1/5 PLLs).

I found one reference on Intel http

To avoid this error insert a Clock Control Block (ALTCLKCTRL) Megafunction between the reference clock pin and both the fPLL and the user logic.

but didn't find such IP in the library.

Thanks for any hints.

  • 2
    \$\begingroup\$ Altera provides a free library of megafunctions, based on both hardware and non-hardware Tcl infrastructure. The library includes I/O Megafunction ALTCLKCTRL. To define and instantiate a megafunction using the GUI, click Tools > MegaWizard Plug-In Manager and follow the wizard to define your megafunction. The Quartus II software automatically generates synthesis and optional simulation output files (see intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/…). \$\endgroup\$
    – V.V.T
    Sep 20, 2021 at 6:34

1 Answer 1


The key part of the error message is:

   Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.

Quartus is trying to place the second PLL in the same location as the first, but can't because either the inputs differ (e.g. different reference clock, different reset signal), or it cannot find a set of parameters that will produce the clocks needed by both PLLs.

As to why they are trying to be placed in the same location, this happens for a number of reasons. Primarily that they have been constrained to the same location for some reason.

PLLs can be finicky things when it comes to placement because they are intrinsically linked with the clock network in the FPGA. This network is a lot less flexible than logic routing, so a lot of care must be taken. Full details about the clock network can be found in the Cyclone V Device Handbook. Specifically for PLLs, pay close attention to which reference clocks can drive them. For your device (Cyclone V SE A4):

Clock sources for the Cyclone V SE A4 devices

Based on the location at X0_Y1 from the fitter message, I can see that you must be using the dedicated reference clocks CLK0, CLK1, CLK2 or CLK3 (specifically the _p pin if single ended, or both if differential).

Notice how the second PLL that can be driven from that side of the device, located at X68_Y1 can only be driven from CLK2 or CLK3. I'm guessing therefore that because it is trying to force two PLLs into that location, you are using specifically either CLK0 or CLK1. As a result, there is only a single PLL that can be used.

To fix this, you will either need to manually merge the PLLs - that is to create a single IP Core Wizard PLL instance that produces both clocks (if possible) which will allow the now single PLL to sit in the correct location. Alternatively, use a different reference clock pin for your second PLL if possible.

If you are using a dev-kit, you will likely find that the same reference clock is fed in to multiple pins in the device for this very reason.

A third, less ideal option exists on the Cyclone V's. The PLLs can be driven from the global clock network instead of a dedicated clock input. The jitter performance in this mode will be worse, but it is usable in a pinch.

To make use of this, either:

  • Feed the clock input of your second PLL using a clock output from your first PLL
  • -or- instantiate an instance of the ALTCLKCTRL IP core with the input connected to your reference clock, and the output connected to the PLL clock input.

Cyclone V PLL Block Diagram

  • \$\begingroup\$ All options you suggested are valuable. I was avoiding the dual output PLL since that doesn't allow me to generate exact frequency recommended by the ADC for mains noise rejection. The ADC performance might be somewhat compromised by jitter too. So the clear winner is utilizing independent clock path. As you eluded the eval board does have the clock routed to multiple pins so routing CLK2P pin through separate path to independent PLL does the trick and allows me to generate exact frequency. \$\endgroup\$ Sep 20, 2021 at 19:02
  • \$\begingroup\$ Many thanks! Definitely saved my day! \$\endgroup\$
    – hansfbaier
    Feb 14, 2023 at 4:59

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