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I'm transferring code from HC9S12DP512 to MC9S12XEP100. But there are some differences that I don't understand, even reading their datasheets.

The configuration is like this:

  ECT_TIOS  |= 0x10;                      /* Make channel an output compare  */
  ECT_TC4    = ECT_TCNT + OSTickCnts;     /* Set TC4 to present time + OS_TICK_OC_CNTS  */
  ECT_TIE   |= 0x10;                      /* Enable OC4 interrupt */

With the above configuration the following lines of code work for HC9S12DP512 but not for MC9S12XEP100.

 BSET  PTT, #$010
 BCLR  PTT, #$010

So, I would like to know why on HC9S12DP512 the above lines work even with Output Compare enabled and on MC9S12XEP100 it doesn't. Below, I have two tables that I took from the HC12 and 9S12X user guide.

Below, I have two tables that I took from the HC9S12DP512 and MC9S12XEP100 user guides.

  • From HC12:

enter image description here

  • From 9S12X

enter image description here

The text is changed just for the 0 / 0 option.

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    \$\begingroup\$ You're asking a specific question on the internal operation of NXP's chips. Surely it would make sense to ask them first? \$\endgroup\$
    – Kartman
    Commented Sep 20, 2021 at 12:42
  • \$\begingroup\$ Yes, I did this too \$\endgroup\$
    – Daniel
    Commented Sep 20, 2021 at 13:02
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    \$\begingroup\$ Owe! That is not nice of them. You must have spent some time to come to that line. Meantime, my interpretation: "The text for the 0 / 0 option" makes sense, though they should not do that, they had to highlight that line on every page. :-) "Timer disconnected from pin logic": A timer (output) does not control the pin, something else does. "No output action on the signal": The timer still owns the pin, as long as the function is enabled. Some microprocessors have very the same arrangements (pin-mux), too. \$\endgroup\$
    – jay
    Commented Sep 20, 2021 at 13:27

2 Answers 2

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Typically when you enable an internal peripheral on a set of µController pins those pins no longer function as GPIO pins. I say typically because I don't know every single µC on the market. But that is generally how they work.

The different peripheral functions for a set of pins are selected via pin-muxing logic in the silicon. Like a switch - it can be in one position or the other but not both.

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I got in touch with an NXP representative and they got back to me. According to him, On S12D, the direct output compare action on pin is defined by TCTL1/TCTL2 configuration. On S12XE, the TCTL1/TCTL2 configuration works similar, but OLx,OMx=0 will not automatically enable GPIO functionality on a pin. You have to additionally set the appropriate bit in the new OCPD register for disconnection port T pin from ECT driving. After that, you may use OC4 channel and GPIO function on PT4 simultaneously.

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