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I have a clock signal coming from an instrument that I need to use to synchronise other instruments. However secondary instruments need to have different phases and I need to be able to sweep the clock period (100 ns > 10MHz) with 1 ns step maximum.

I managed to sweep 20 ns with an FPGA programmable DLL (minimum clk input 32 MHz so I used 50 MHz as multiple of 10 MHz), but I still have 80 ns that I can't sweep. FPGA DLL step is FREQ(50MHz)/256 ~ 80 ps.

I am looking for an IC reference of a PLL or DLL in which I can program the phase during runtime. I also accept alternative solutions.

I searched for programmable delay, programmable phase shifter, programmable PLL, however I couldn't find anything that could help me.

To illustrate, the image below shows a clock with different phases with 90 degrees step, I need around 3 degrees step maximum 3*(100 ns/360) ~ 830 ps. If I can have more precision is even better.

enter image description here

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  • \$\begingroup\$ It's not clear what you are asking for (I don't understand nothing) \$\endgroup\$ Sep 20 at 15:53
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    \$\begingroup\$ Would something like the Si5351 work (programmable clock generator with per channel delay)? If not, probably something in the Si catalog does that. \$\endgroup\$ Sep 20 at 15:53
  • \$\begingroup\$ 830ps resolution needs over 1.2 GHz operation. It sounds better than the last question, asking a few ps resolution. If you can explain what you are doing with that, you may have better solution. \$\endgroup\$
    – jay
    Sep 20 at 15:54
  • \$\begingroup\$ @user1850479 I already have a clock source. I need to have a copy of the same clock with different phases. \$\endgroup\$
    – Raphael
    Sep 20 at 16:00
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    \$\begingroup\$ Have you considered a programmable delay line such as this? maximintegrated.com/en/design/technical-documents/app-notes/1/… The DS1020-015 has 150ps resolution per step. \$\endgroup\$
    – jwh20
    Sep 20 at 16:18
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Let me recommend a programmable delay line such as this?

https://www.maximintegrated.com/en/design/technical-documents/app-notes/1/107.html

The DS1020-015 has 150ps resolution per step

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  • \$\begingroup\$ Hi. I bought a similar IC (DS1023) with 250 ps step resolution. It does exactly what I want. Thank you very much for your time and help. \$\endgroup\$
    – Raphael
    Oct 8 at 6:33
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I assume this clock is distributed over cables since you are connecting different instruments. I should point out that cable lengths should be accounted for at the time scale you seek to control. About 3ns per meter of cable is a rule of thumb. If you want 1ns shift in reference to the source instrument, then the cable might already exceed your requirement when it arrives at the receiver instruments. If the two instruments must be synchronized at that level, then a master clock source should drive both instruments so any delays from cables are canceled out and any delay you inject to one cable is preserved relative to the other.

If this is for an important experiment/development and reliability is a factor, then I would suggest a delay generator such as the SRS DG645 that is designed to take an input and provide picosecond delay outputs. Input frequency maximum for the DG645 is 10MHz IIRC. The delay generator circuit is a mix of analog and digital delays in order to properly create delays that are synchronous to the source even if it is a single event.

A more IC based option are programmable delay lines such as the Maxim DS1020-100 with a 1ns step and 256 steps. Note that a 0 step still incurs a 10 ns latency between input and output. There are other step sizes in that family down to 150ps.

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  • \$\begingroup\$ Hi, thanks for you answer. The initial delay is not important, I need to be able to perform delay over one clock period, doesn't matter the start point, so the cables are ok if they introduce an additional delay. I have a function generator with 40 ps delay step if I am not mistaken. The problem is that the clock from the instrument is around 10.2MHz and the FG accepts only 10 MHz +- 35 kHz as EXT REF. And when I insert the clock as trigger to create a burst I can managee to trigger only 2.5 MHz. \$\endgroup\$
    – Raphael
    Sep 20 at 17:03

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