In the CD4013B datasheet the following timing table (excluding clock related values) can be found:

enter image description here

According to the answer to this question, the contamination delay would be the minimum propagation delay, which makes sense, but this range is not provided in the table.

If one CD4013 FF Q is connected the D of another CD4013 FF with the same clock (and this obviously work) one has to guarantee that the output is held for at least the specified \$t_{hold}\$ time before it starts changing and stops changing at least \$t_{setup}\$ before the next clock.

Ok, the clock parameters are given (and were ommited in the print above) but I'd like to know if the "contamination time" mentioned in many books and classes is the same as the "transition time" in the datasheet.

Edit: to be clear, I'm referring to the "clock to Q contamination time". Inferring it from the clock specs would work for the same component (as mentioned above) but not for interfacing with different components.

Edit 2: in the mean time I found another author which not only confirms what was shared in the comments (regarding the absence of the term in datasheets) but also expresses my concern better than what I managed to do (source in the image):

enter image description here

I've found two other datasheets (for the 4013) which also do not inform the minimum propagation delay. I also failed to find a definition for what I'm searching at the relevant JEDEC standard (which includes clear definitions for what appears in the datasheets).

Question: since it is not \$t_{cd}\$, what parameter guarantees that the \$t_{hold}\$ of the next component, operating with the same clock, is respected? I'm obviously missing something very fundamental since this is ignored everywhere, so, please point me to the right concept.

  • 2
    \$\begingroup\$ You should know that "contamination delay" is not a term that is commonly used in industry. It seems to have arisen from the Harris book on digital design and is fairly unique to that author. \$\endgroup\$ Commented Sep 25, 2021 at 14:30
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    \$\begingroup\$ Sorry to sound the old soldier but in many decades in electronics, dealing with a large number of people in many industries, I've never once heard the term 'contamination delay'. I would forget that term as fast as possible, you'll only cause confusion with it. \$\endgroup\$
    – TonyM
    Commented Sep 25, 2021 at 14:53
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    \$\begingroup\$ Contamination delay is a bizzarre and unneccessary term, presumably created to simplify something. In 40 years of designing logic, I have never needed the term. Propagation delay, setup and hold times, which are found in data sheets, min/max as appropriate, typical if you're feeling lucky or stupid, are all you ever need for a robust and comprehensible design. \$\endgroup\$
    – Neil_UK
    Commented Sep 25, 2021 at 15:09
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    \$\begingroup\$ contamination delay in simpler words is 'minimum propagation delay'. \$\endgroup\$
    – Mitu Raj
    Commented Nov 4, 2021 at 16:50
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    \$\begingroup\$ If datasheet is giving only typical value, I would probably assume a derate factor/uncertainty of 10% - 20% or so and use them to range: (min, max) and then use them to do setup/hold timing analysis. But this could depend on PVT conditions. @devnull \$\endgroup\$
    – Mitu Raj
    Commented Dec 2, 2021 at 11:59

2 Answers 2


The problem is that the information on the time guarantee between a clock edge and the beginning of change at the output seems to be important.

In the particular datasheet you referenced, the delay between a clock edge and a change in output is called "Propagation delay time". They are labeled as TPHL or TPLH depending on if the output is transitioning from low-to-high or high-to-low. It is in the first row of the table in the datasheet section labeled "6.6 Electrical Characteristics: Dynamic".

since it is not tcd, what parameter guarantees that the thold of the next component

To have a guarantee they would need to publish a minimum value for TPHL and TPLH. For this particular chip they only publish typical and max values, so you really don't have a guarantee.

You could email Texas Instruments customer support, or use their TI E2E forum and ask if they have an unpublished number for the minimum TPHL/TPLH for this chip.

If they don't have a number, then you have two choices.

  1. If the next chip has an input hold time of 0ns or less, then just assume that. Its a perfectly safe assumption since the the propagation delay can't be less than 0ns without violating causality.

  2. Assume something much less than typical. For example, at 5V, this chip has a propagation delay of 150ns typical, and a maximum hold time of 5ns. 5ns is 30X shorter than 150ns. The chances of the delay being 30X lower than typical is probably pretty small, so you are most likely safe if you wanted to feed the output of one chip into another identical one.


Wikipedia redirects queries for 'transition time' and 'fall time' to the article 'Rise time', which it defines as 'the time taken by a signal to change from a specified low value to a specified high value.' Application notes mention two types of transition time, input transition time and output transition time, as the transition time at the input and at the output, respectively. When a modifier input/output is not specified, as in the CD4013B datasheet of your reference, it is the transition time at the output.

A good characterization of contamination delay in its relationship with propagation delay is given in Cadence's article Contamination Delay in Clock Circuits: Best PCB Routing Techniques:

Contamination delay is the minimum time required after a change to the input before the output begins its initial change. Propagation delay, on the other hand, is the maximum amount of time needed for the output to finish its change in value.

So, taking for example the case of a rising signal at the input and a rising signal at the output, 'contamination delay' can be the time interval between a moment the input signal reaches 80% (90%) of its final value, finishing its transition, and a moment the output signal reaches only 20% (10%) of its final value, at the very beginning of its transition period.

Summing up, contamination delay is not a transition time.


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