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When measuring the voltage transfer curve of an 74HC04 a small hysteresis was observable.

transfer function

The input voltage is plotted on the X-axis, while the output voltage is indicated by the Y-axis, unit is volt.

Is there a technical reason for the measured hysteresis?

My assumption was, the 74HC04 is not equipped with a schmitt trigger (which should result in a more pronounced transfer function nevertheless), also the datasheet does not reveal anything regarding this.

Many thanks for your input!

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    \$\begingroup\$ how did you measure ? What was the load ? The 74HC04 has quite high gain and it may have possibly been oscillating. This will cause anomalous measurements. \$\endgroup\$
    – jp314
    Sep 25 at 22:58
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    \$\begingroup\$ This does not seem really "hysteresis". It seems only a different "behavior" when going from one state to the other. \$\endgroup\$
    – Antonio51
    Sep 26 at 7:15
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    \$\begingroup\$ One more point to make. The behavior of most CMOS digital parts is not specified in the transition region. The vendor guarantees certain performance if the input voltage is less then Vin(l), and greater than Vin(h), but doesn't promise anything for Vin(l)<Vin<Vin(h). \$\endgroup\$
    – SteveSh
    Sep 26 at 11:48
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Many CMOS devices indeed have a small amount of hysteresis. For example, TI's AHC application note says:

Input hysteresis of typically 150 mV is included in AHC devices (300 mV in AHCT devices), which ensures the devices are free from oscillations by increasing the noise margin around the threshold voltage during low-input transitions.

AHC hysteresis

For fast devices, the inductance of the bond wires could slow down the input signal and the supply current spikes enough to shift the input threshold and cause oscillations. The hysteresis prevents that.

It's not enough to prevent osciallations when the input signal has slow edges, and much smaller than with 'real' Schmitt-trigger inputs. Therefore, it is typically not mentioned in the datasheet,

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The 74HC04 has 'buffered' NOT gates, which means each one is actually 3 inverters in series (one to invert the signal, and two to buffer it without undoing the inversion). As a result the gain from input to output in the transition (linear) region is very high.

Each inverter has a propagation delay due to resistance and capacitance of the FETs, which forms a low pass filter. In the linear region this causes a phase shift that approaches 90° as frequency increases. The gate can oscillate if the total phase angle (including the 180° inversion) gets to 360° while there is enough feedback (eg. through the power supply or external wiring) and gain to create a loop gain greater than 1.

With a single unbuffered gate this is unlikely to occur because the total internal phase change can't exceed 270°. However with 3 inverters in series each one only has to contribute 60°, at which frequency they may still have enough gain to overcome feedback loss. In practice this means that oscillation is almost guaranteed during slow transitions (which is one reason to use gates with Schmitt Trigger inputs for slowly changing logic signals).

I tested one gate in a 74HC04 by connecting a potentiometer to the input and varying the voltage while watching the output on my oscilloscope. When using a 10 kΩ pot the results were similar to yours, except that I saw a strong high frequency oscillation in the middle region.

When I changed the pot to a 5 kΩ unit the oscillation was much weaker and the hysteresis all but disappeared. The input voltage variation from full high to low output then reduced to ~30 mV. However the input was still very sensitive to noise. I had to isolate the multimeter with a 10 kΩ resistor in series to avoid disturbing the output when measuring input voltage.

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On simulator or using a X-Y scope, one can see this ... and it is not hysteresis. 1 pF and 10 kOhm added.

You can also see some oscillations on transitions. These can disappear if using a additional capacitor on input.

enter image description here

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