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First I'll write the definition I know for things Im gonna mention in my question.

Given a flip-flip, a setup time is the amount of time the synchronous input must show up and be stable, before the capturing edge of clock.

hold time is the amount of time the input data must be stable after the active edge of clock.

Now, I know that in general when we have 2 flip-flops and combinational circuit between them, as described here:

enter image description here

(C is combinational circuit), the following has to hold:

$$ tpd(FF)+tpd(C)+t_{setup}\leq T $$

Where T is the clock period. (The explanation is that input from the first FF takes \$tpd(FF)\$ time to be stable in the entrance of \$C\$ and then \$tpd(C)\$ to be stable in the entrance of the second FF, and there it must be stable for \$t_{setup}\$ amount of time).

Now if we consider the following system:

enter image description here

Where FA is a full adder part, and JK flip-flop excitation table given by:

enter image description here

and we call this system a B-flipflop with input \$ x \$ and output \$z\$, Im not sure how to calculate its setup time. I'll show 2 possible answers that I cannot tell which is the correct one:

  1. As I showed in the general case, when the input of the flipflip being measured by the clock, it take \$tpd(JK-FF)\$ time for it to be stable at the output, and the it takes \$(tpd(FA))\$ time to be stable at the output of the FA, and the it must be stable for more \$t_{setup}(JK-FF) \$ time. So it seems that the setup time should be the sum of all of those.

But if Im asking myself how much time should the input \$x\$ be stable before a clock measure, it would be just \$ tpd\left(FA\right)+t_{setup}\left(JK-FF\right) \$.

So question is, do we need to consider all of the entrances of the FA or just the \$x\$ input?

I'd really appreciate an explanation because I get confused everytime with this type of questions. Thank in advance.

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The detailed answer is that a circuit like a full adder has a whole matrix of propagation delays, each measured from one specific input to one specific output. You need to consider each of those delays. For example, the FA will have a delay from \$x\$ to its S output, which you'll combine with the JKFF's setup requirement on its J input. There will be a different delay from \$x\$ to the FA's Cout output, which you'll combine with the JKFF's K setup requirement. For the circuit to work reliably, the clock period must be greater that the worst case delay among all of these paths.

You can see that the number of paths that need to be considered grows rapidly with the circuit complexity, which is why we use static timing analysis tools (software) to handle anything other than the most trivial circuits.

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