So I'm trying to create a FSM elevator system (single elevator 5 floors) in SystemVerilog and I'm having trouble mapping out how to write the code. In a traditional Moore or Mealy style FSM I can see that the combinational logic is separated from sequential but in this problem it doesn't seem to fit into that template.

My algorithm is pretty simple where there are two queues or memory storage pools. The pool of requests (internal or external) which can be satisfied in the current elevator path and then the separate pool of requests that cannot be and will only be satisfied once the elevator changes direction. In that case, the queues or memory storage pools will be reversed in which case the previously un-servicable queue will now the serviceable queue and vice versa.

The main problem apart from general design confusion is that I need to keep a storage of the inputs so I need some notion of memory. I'm thinking of using registers to store status of each floor request (both internal and external).

The other inputs (other than internal and external floor requests) to the FSM are current floor and CLK. Outputs are Motor on, Motor direction, and next floor.

I know the general Moore FSM coding style is to separate next state from output logic and have always_comb statements for both next state and output logic blocks. But in my case it seems like the problem is more than a simple FSM, and it involves a datapath. How can I break apart this problem and modularize it so that I can clearly write the code in a structural format (block diagrams) rather than behavioral which I know will be prone to many error since I'm not following a standard template.

  • \$\begingroup\$ Please provide some code, otherwise it will be hard to provide any meaningful help or advise. \$\endgroup\$
    – andrsmllr
    Sep 30, 2021 at 9:55

1 Answer 1


The question is not concise; Here are some ideas to help with your design:

Model each of the "queues" as an array (sometimes called an unpacked array) of 1-bit registers using a clocked process.

// assuming you have 8 floors
logic hall_requests [7:0];
logic internal_elevator_requests [7:0];

I put "queues" in quotes becase SystemVerlog has a data type called a queue, an it would be easy to mix them up. Don't try to use the SV queue for your RTL design it's intended for testbenches.

Have two arrays of control bits for each request, one array to set the request for a corresponding floor, the other bit to clear it.

logic set_hall_requests [7:0];
logic clear_hall_requests [7:0];

logic set_internal_elevator_requests [7:0];
logic clear_internal_elevator_requests [7:0];

The set_xxx bits are inputs to the controller from the testbench. The clear bits are outputs from your SM. This is basically modeling an array of RS flip flops. The array allows each to be indexed by a count (next_floor).

Create a synchronous count for the current_floor and a count for the next floor. int current_floor; int next_floor;

Make the current_floor a register, and reset to 0 at startup.

Have a single register to keep track of the direction. logic up_ndown;

Motor control signals should fall out of the above.

A reset input is needed to start initialize the request_arrays, state machine and counters and direction.

One function of the state machine is to index into the request arrays starting at 0, and find the next bit that is set, and that becomes the next floor. Have a state called FIND_NEXT_FLOOR. Also, have a state called ASSIGN_NEXT_FLOOR, another WAIT_SO_PEOPLE_CAN_GET_ON_OFF, and one called WAIT_FOR_ELEVATOR_TO_TRAVEL (assuming it does not travel in 0 time). Also a HOME or INIIAL state.

A unique state could be used to check each floor, if so then jump to ASSIGN_NEXT_FLOOR when you find a logic 1. In this case 8 states are used just to determine the next_floor. Otherwise a case or nested if could be used within the ASSIGN_NEXT_FLOOR state. It might be easier to draw a state diagram if you have a state per floor, otherwise you are faced with how to represent case/nested if statements on a drawing.

There is no pipeline in this design, only some registers and counters that need to be synchronously set and cleared by a state machine. A example of a data pipeline would be the input data and it's delays in an FIR filter.

The normal SM template works.

It is a Mealy machine since it takes input.

I like to code SM's with two processes one synchronous to assign the

current_state <= next_state

and another to assign the output logic and next state.

  • \$\begingroup\$ We try not to hand out solutions to homework problems here. We expect the OP to demonstrate that they have put forth a substantial effort to solve the problem themselves, and then to ask a specific question. \$\endgroup\$ Sep 27, 2021 at 15:31
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    \$\begingroup\$ These are tips and somewhat abstract concepts, its not a complete solution. \$\endgroup\$
    – Mikef
    Sep 27, 2021 at 15:32
  • \$\begingroup\$ Hi mike. Could you please help me understand how the components are connected in a block diagram? I'm not sure how the registers, RS flops, and counter indexes fit together. Also I don't understand the logic for indexing requests using a counter. \$\endgroup\$
    – James Dean
    Sep 29, 2021 at 19:20
  • \$\begingroup\$ I'm also not sure why we need the array of registers if we can use the RS flip flops to keep track of the incoming requests. Thanks \$\endgroup\$
    – James Dean
    Sep 29, 2021 at 19:56
  • \$\begingroup\$ The block diagram (the other post) is not a block diagram its more of a schematic ;it shows the interconnection. The array of registers has an index, the index is used to select which one currently active. The state machine needs to loop over them all to determine which one is active. The registers are RS flops. More precisely they model the behavior of RS flip flops in SystemVerilog code. Don't instantiate RS flip flops, model them using if statements in clocked processes. Have an array to make it easy to change the number of regs & loop over them by changing the index/count. \$\endgroup\$
    – Mikef
    Sep 30, 2021 at 18:58

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