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Counter

We can get the same result (counting from 0000 to 1111) by removing the last flip-flop (Q3 output) and taking clock line as one of the inputs (i.e Q0 will be from clk itself and rest 3 outputs from 3 flip-flops.) This reduces the number of flip-flops.

Are there any disadvantages to this or is it impractical?

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    \$\begingroup\$ When clock signal disapear you will lost this one bit (LSB). With 4 FF you have a stored number. \$\endgroup\$ Sep 27 at 7:31
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    \$\begingroup\$ Clock signal may disappear but power must remain applied for FFs to retain their state. n FFs can hold a maximum of 2^n states. Indeed for asynch circuits clock pulse will be produced by some activity every once in a while such as a person entering a doorway or a car entering a garage etc. \$\endgroup\$
    – Syed
    Sep 27 at 7:46
  • \$\begingroup\$ Oh nice, Thanks. \$\endgroup\$
    – Manish
    Sep 27 at 8:10
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The point of the counter is to count the number of clock cycles it has seen. If the clock stops, the counter will remember the number of counts.

If you use the clock as one of the outputs, then that isn't counting anything; it's just the clock. If you set the clock low for a long period, then that first output would be low, and tell you nothing about how many clock cycles there have been.

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  • \$\begingroup\$ Thanks, Got it ! \$\endgroup\$
    – Manish
    Sep 27 at 8:11
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Consider what the purpose of this counter is in the larger circuit. If the purpose is to generate the four "counting"-waveforms, and if you can guarantee that the clock signal is well controlled with a 50% duty-cycle, then yes, you could concivably use a 3-bit counter.

However, the output of a counter like this is usually used as an input to some other circuit (such as a decoder, or as an adress to some sort of memory). In these cases, you want a full clock-cycle to elapse for each combination of the output lines, so that the larger circuit can do something with each of the combinations. This requires the clock-signal as an extra signal, and requires the least-significant bit of the counter value to oscillate at one-half the frequency as the clock.

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What you describe is entirely correct. Whether it's useful or not depends on your application.

If you don't care about the clock duty cycle (see the answer by sondre99v), then with four flip-flops you actually have five signals counting from 0 to 31.

Since you have many devices connected to the clock, you may find that its transitions are somewhat sluggish compared to the flip-flop outputs, but there's nothing wrong with your logic here.

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