3
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So I know how to instantiate multiple instances of the same component in VHDL, see the example code:

  component REG
    port(D,CLK,RESET : in  std_ulogic;
         Q           : out std_ulogic);
  end component;
begin
   GEN_REG: 
   for I in 0 to 3 generate
      REGX : REG port map
        (DIN(I), CLK, RESET, DOUT(I));
   end generate GEN_REG;
end GEN;

I want to know if it's possible to retrieve the instantiation number within the code, so which "I" belongs to which instantiation, from within the instantiated code.

edit: I want to use the instantiation number, because that is also the address for which device I want to address. So I'm creating an x number of instances, each for a certain device interfaces. It would simplify some stuff when the instance itself knows which instance number it is.

edit2: Can I generic map I to some integer generic?

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3
  • \$\begingroup\$ not clear to me what you want – I is the number of the instantiation. \$\endgroup\$ Sep 28 at 12:50
  • \$\begingroup\$ This "address" is going where? It is supposed to be "carved" in some hardware, right? Like certain wires that are going from the master to a specific slave device. So generate this hardware within this loop. Best way to describe what you are trying to do is draw a schematic showing the wanted generated topology. \$\endgroup\$
    – Eugene Sh.
    Sep 28 at 13:20
  • 1
    \$\begingroup\$ Generic map ought to work just fine. \$\endgroup\$ Sep 28 at 16:09
7
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You can create an integer generic on the instantiated component and pass it the loop control variable value.

Then your instance can use the generic value to distinguish itself from the other instances.

  component REG
    port(D,CLK,RESET : in  std_ulogic;
         Q           : out std_ulogic);
  end component;
begin
   GEN_REG: 
   for I in 0 to 3 generate
      REGX : REG generic map (n => I)
        port map
        (DIN(I), CLK, RESET, DOUT(I));
   end generate GEN_REG;
end GEN;
\$\endgroup\$

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