# MUX verilog code

Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it.

module decoder_24(in1, in2, out1, out2, out3, out4);
input in1,in2;
output out1,out2,out3,out4;
assign  out1 =!(!in2&!in1);
assign  out2 =!(!in2&in1);
assign  out3 =!(in2&!in1);
assign  out4 =!(in2&in1);
endmodule

module multiplexer41_4bit(input0, input1, input2, input3, sel0, sel1, out);
input [3:0] input0,input1,input2,input3;
input sel0,sel1;
output [3:0] out;

//multiplexer0
multiplexer_41 M41_0(input0[0],input1[0],input2[0],input3[0],sel0,sel1,out[0]);

//multiplexer1
multiplexer_41 M41_1(input0[1],input1[1],input2[1],input3[1],sel0,sel1,out[1]);

//multiplexer2
multiplexer_41 M41_2(input0[2],input1[2],input2[2],input3[2],sel0,sel1,out[2]);

//multiplexer0
multiplexer_41 M41_3(input0[3],input1[3],input2[3],input3[3],sel0,sel1,out[3]);
endmodule


Second:

case({m_sel2,m_sel1})
2'b00: m_out = m_in1;
2'b01: m_out = m_in2;
2'b10: m_out = m_in3;
2'b11: m_out = m_in4;
default: m_out = 1'b0;
endcase

• do you have the code for the multiplexer_41 module? – The Photon Feb 22 '13 at 18:08
• I am trying to post it but the it comes out in a very bad format for some reason. will try to fix it and send it over soon – sotiris Feb 22 '13 at 18:41
• case({m_sel2,m_sel1}) 2'b00: m_out = m_in1; 2'b01: m_out = m_in2; 2'b10: m_out = m_in3; 2'b11: m_out = m_in4; default: m_out = 1'b0; endcase – sotiris Feb 22 '13 at 18:44
• @sotiris - Use the edit button to add the code to the original post. You're currently adding it as a 'comment', which has a different purpose. – Tim Feb 22 '13 at 20:24
• nice one Tim. quite new here – sotiris Feb 22 '13 at 20:28

Your first module, decoder_24, is a decoder. It has 2 inputs and 4 outputs. It asserts exactly one of the outputs, depending on what combinations of inputs is asserted.

Your second module, multiplexer41_4bit, is a multiplexer. It has 4 data inputs, 2 select inputs, and one output. The data inputs and the output are each 4 bits wide. Depending on what combination of select lines are asserted, the one of the data inputs is passed through to the output.

How it works, is there's 4 single-bit multiplexers in parallel. Each one is controlled by the select lines, and has its data inputs connected to one bit of each of the 4 data inputs and its output connected to one of the bits of the output. As for how the one-bit multiplexers work, you need to look at the multiplexer_41 module to find out.

• Thank you. Helpful comment. However still kinda lost you at the end. I think if you try to explain me what the numbers in the brackets mean will get it. for example at the line below what number 3 represents? input0[3] – sotiris Feb 22 '13 at 18:40
• When you declare input [3:0] input0, you are saying that input0 is a bus with 4 wires. The individual wires are input0[0], input0[1], etc. – The Photon Feb 22 '13 at 18:57
• @sotiris That's the index of the bit that you're passing (zero based of course). – Jeff Langemeier Feb 22 '13 at 18:57

If someone can explain how the second one works would much appreciate it.

case({m_sel2,m_sel1})
2'b00: m_out = m_in1;
2'b01: m_out = m_in2;
2'b10: m_out = m_in3;
2'b11: m_out = m_in4;
default: m_out = 1'b0;
endcase


Lets consider, that all signals (m_sel2, m_sel1, m_out, m_in1, m_in2, m_in3, m_in4) are 1 bit long.

Tnen {m_sel2,m_sel1} - is concatenation of two signals m_sel2 and m_sel1. If m_sel2 = 1'b0 and m_sel1 = 1'b1, then {m_sel2,m_sel1} will be equal to 2'b01.

Case statement synthesizes into a multiplexer. If think for a while about how case works - you will find, that it is pretty much the same as mux.

As for the realization: Case statement is a Behavioral Statement, and it must be inside Procedural Block. So I added some minor code:

module mux_4x1(m_sel2, m_sel1, m_in1, m_in2, m_in3, m_in4, m_out);
input m_sel2, m_sel1;
input m_in1, m_in2, m_in3, m_in4;
output reg m_out;

always @(m_sel2, m_sel1, m_in1, m_in2, m_in3, m_in4)
begin
case ({m_sel2, m_sel1})
2'b00: m_out <= m_in1;
2'b01: m_out <= m_in2;
2'b10: m_out <= m_in3;
2'b11: m_out <= m_in4;
default: m_out <= 1'b0;
endcase;
end
endmodule


So I went a little bit further and made simple project in Altera Quartus II. I think, that with Xilinx FPGA there will not be much differences.

After building a project we can see the result in a rtl-viewer.

Compilation Summary tells us, mux project uses 2 4-input LUTs. For better understanding about how mux is created on LUTs, you can look at this:

Here LUTs functions are represented as scheme.

I hope that I did not confuse You even more!