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I would like to simulate this buffer in LTspice 74ABT244PW. I already got its model under the "support" section of the link. Now I'm new to LTspice and I had experience adding models before but how I did it in the past I first add a base component and make a directive from the external then link the base component to the directive. But now there is no buffer in the component list.

enter image description here

So how do I simulate that buffer component?

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  • \$\begingroup\$ Have you tried searching for the part itself (maybe LTSpice doesn't support too many logic chips?) \$\endgroup\$
    – Andy aka
    Sep 29, 2021 at 11:14
  • \$\begingroup\$ @Andyaka No 74abT244 showed up when i type it in the search box of the image in the question. Are there other ways to search components im not aware of? \$\endgroup\$
    – DrakeJest
    Sep 29, 2021 at 11:34
  • \$\begingroup\$ You can probably choose an AC version or HC version and tweak the timings. \$\endgroup\$
    – Andy aka
    Sep 29, 2021 at 12:48

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Their page has an archive with a SPICE model (not the IBIS one). In it there are two folders, HSpice and PSpice -- the latter is the one you're looking for, since LTspice is, mostly, PSpice compatible.

Inside there are a few library files (*.lib) containing lots of subcircuit definitions, many of them being used inside the actual model for the gate. It can look daunting, but there is also an abtps.cir file, which is a test circuit that can be readily opened up in LTspice, and simulated. It has no visual schematic because it's nothing but a netlist, but it does list the possible .lib combinations you need in order to build you own schematic, including some other files.

In this case, it shows that in order to use the 74ABT244 you need to add:

  • the ABT family library with .lib abtpsub.lib;
  • the relevant package -- choose between lib so.s, .lib ssop.s, or .lib tssop.s;
  • the default parameters with .lib abtpnom.lib, or the fast ones (abtpfas.lib) or slow ones (abtpslw.lib). The differences should be in the level of detail with which the device is made at transistor-level. The nominal should do.

I don't know what and how you did it, but if you say you see no symbol it's because there is none included; you'll need to create one, yourself. Or autogenerate one, if it's to your liking.

One thing to notice: the test file (abtps.cir) uses a global net, $G_VCC, inside their subcircuits. Since you say you're new to this, a net name that starts with $G_ means it's global and is available at any level in a hierarchy, or subcircuits (i.e. here, $G_VCC used inside the libraries will be available at the "surface", or in the top level schematic); otherwise, labels are only available to the current level (i.e. a node named X inside a subcircuit will not be visible outside of it, and using the same X notation outside the subcircuit will not clash with the subcircuit one). I'm saying this to be careful when using that name.

So, for your case, here's one way to use the GUI to replicate their test file:

test

I haven't created any symbol, manually or autogenerated; instead, I used the readily available [Misc]/tetrode, because it already has 4 pins. If you look in their test circuit, the relevant line for the subcircuit is:

XABT244       2       4       $G_VCC      0       BUFFER2

so any symbol with 4 pins will do. The order of the pins is input, output, positive supply, and negative supply -- that's how you see it now connected. But, since their test doesn't use a symbol (a netlist doesn't need one), you can circumvent that by adding a SPICE directive (S key) with the line that you see commented out, above (in blue text); that will substitute the need for a symbol.

Another difference is their usage of $G_VCC. I avoided that to show that it's not mandatory to use it, since my power supply uses, simply, VCC. But the availablility of $G_VCC remains, and if I were to connect something else with that node, it would interfere with the symbol -- so, be careful!

About the last difference would be the usage of the simulation card: .TRAN 500p 50n vs my .TRAN 50n. The former notation makes use of the legacy way of defining the simulation command (you can see it in the LTspice's help: LTspice > Dot Commands > .TRAN). In short, the 500p should add a hint to the solver about the timestep that should be used, but, as the manual says:

The first form is the traditional .tran SPICE command. Tstep is the plotting increment for the waveforms but is also used as an initial step-size guess. LTspice uses waveform compression, so this parameter is of little value and can be omitted or set to zero.

Emphasis mine. Therefore I used the latter form.


Alternatively, if all you need is some digital buffer, I'd recommend [Digital]/buf, or [Digital]/inv, [Digital]/schmitt, or [Digital]/schmittinv. See the help under LTspice > Circuit Elements > A. [...] for more settings.

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  • \$\begingroup\$ To add the library i need the ltspice file to be in the same folder as the library? Also how did you navigate to find the tetrode? I actually need to simulate this specific IC as this is the one i will use, i need to simulate the 4 channel in parralell. How to do that? do i just make 4 copies of the tetrode in your circuit? \$\endgroup\$
    – DrakeJest
    Sep 29, 2021 at 13:36
  • \$\begingroup\$ I think i have everything inplace, but im lost on how to link the tetrode the model. Image \$\endgroup\$
    – DrakeJest
    Sep 29, 2021 at 13:51
  • \$\begingroup\$ Okay i was able to simulate, Quick question why is the output voltage so low? that does not feel right \$\endgroup\$
    – DrakeJest
    Sep 29, 2021 at 14:24
  • \$\begingroup\$ @DrakeJest The datasheet specifies the minimum output logic high to be 3 V (for Io=3 mA, and here it's ~6 mA after the cap is charged, and 120 mA peak). Since the load is 500 Ohms, that is quite a high load, which means that 3.5 V that you see there can be very real. Of course, the actual output can only be verified on the breadboard, and any simulation is only as good as the models they use. Don't forget that the specs between samples can differ, too. \$\endgroup\$ Sep 29, 2021 at 14:32
  • \$\begingroup\$ I have 4 in parallel in my setup so im expecting a bit higher voltage, weird paralleling 4 of the buffers seems to have no effect. \$\endgroup\$
    – DrakeJest
    Sep 29, 2021 at 15:00

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