Why is my code output always showing 0?

Question

This is a 4 bit counter code written using Verilog HDL on Quartus. Can somebody explain why is my output o always showing 0?

Code in Text :

module ab(i,o,r);
input i,r;
output [3:0]o;
counter4bit c4(i,o,r);
endmodule
module counter4bit(clk,y,reset);
input clk,reset;
output reg [3:0]y;

always@(posedge clk, posedge reset)
if (clk == 1)
y <= y + 1;

else if (reset == 1)
y <= 0; 

endmodule 

If I write the reset condition first inside the always block it seems to run fine:

if (reset == 1)
            y <= 0;
            else if (clk == 1)
            y <= y+1; 
      )

Answer 1

From your waveform image, it looks like your reset signal (r) is always 0. Since you are not properly resetting your counter, I would expect the output to be unknown (X) instead of 0. I can't explain why the waves show 0 because I am not familiar with Quartus tools.

However, you should really set the reset signal to 1 at time 0, then set it to 0 after a couple clock cycles (say at time 20ns). This should properly reset the counter.

Your always block is not the traditional way to code a counter. You should not check the clock signal inside the block that way. The conventional way is as follows:

always @(posedge clk, posedge reset) begin
    if (reset == 1) begin
        y <= 0;
    end else begin
        y <= y + 1; 
    end
end