# Why is my code output always showing 0?

This is a 4 bit counter code written using Verilog HDL on Quartus. Can somebody explain why is my output o always showing 0?

Code in Text :

module ab(i,o,r);
input i,r;
output [3:0]o;
counter4bit c4(i,o,r);
endmodule
module counter4bit(clk,y,reset);
input clk,reset;
output reg [3:0]y;

always@(posedge clk, posedge reset)
if (clk == 1)
y <= y + 1;

else if (reset == 1)
y <= 0;

endmodule


If I write the reset condition first inside the always block it seems to run fine:

if (reset == 1)
y <= 0;
else if (clk == 1)
y <= y+1;
)


• Make it easier for us to help you. Edit your question and copy the code directly into it, not as a image, so that we can copy it. Do you have testbench code as well? If so, add that to your question. Sep 29, 2021 at 20:38
• @toolic I'm sorry I don't know what the "testbench code" is . I'm very new to this Verilog coding actually. Sep 29, 2021 at 20:45
• It's good that you posted your actual code now. I added formatting for the code for you. In the future, you should try to format it yourself. I'm not familiar with Quartus tools; my guess is that it automatically creates a testbench for you so that you can run a simulation to generate those waveforms. Sep 29, 2021 at 20:48
• Thanks for the edit. From next time I will keep these things in mind. Sep 29, 2021 at 20:58
• @AkibAhmed I gather you want a clocked FF with an async reset? If so, you test the asynchronous reset signal first. Then, I think it can be synthesized. Otherwise? Do you know of an FF that checks its clock before an async reset? Maybe someone has built one. But I don't think it can be readily synthesized. (Probably can be simulated, though.)
– jonk
Sep 29, 2021 at 21:11

From your waveform image, it looks like your reset signal (r) is always 0. Since you are not properly resetting your counter, I would expect the output to be unknown (X) instead of 0. I can't explain why the waves show 0 because I am not familiar with Quartus tools.

However, you should really set the reset signal to 1 at time 0, then set it to 0 after a couple clock cycles (say at time 20ns). This should properly reset the counter.

Your always block is not the traditional way to code a counter. You should not check the clock signal inside the block that way. The conventional way is as follows:

always @(posedge clk, posedge reset) begin
if (reset == 1) begin
y <= 0;
end else begin
y <= y + 1;
end
end