This is a 4 bit counter code written using Verilog HDL on Quartus. Can somebody explain why is my output
o always showing 0?
Code in Text :
module ab(i,o,r); input i,r; output [3:0]o; counter4bit c4(i,o,r); endmodule module counter4bit(clk,y,reset); input clk,reset; output reg [3:0]y; always@(posedge clk, posedge reset) if (clk == 1) y <= y + 1; else if (reset == 1) y <= 0; endmodule
If I write the reset condition first inside the
always block it seems to run fine:
if (reset == 1) y <= 0; else if (clk == 1) y <= y+1; )