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I am a mathematician, so please forgive my wrong terminology :)

I am currently trying to build an 74181 ALU and went over the schematics. On Wikipedia it is given as: https://en.wikipedia.org/wiki/74181#/media/File:74181aluschematic.png

The gate that leads to the C_{n+4} output bit is an OR-gate that has 2 negated inputs and whose output is negated to produce the required bit. This is equivalent to an AND-gate.

(DeMorgan: !(!a||!b) = a&&b).

Can anyone explain why this is used instead of an AND-gate? It puzzles me a lot.

Thanks!

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It's largely a matter of consistency.

Note the top half of the schematic. It uses an AND/OR structure.

The bottom half has a row of ANDs, mostly connected to XOR gates. In the case of the Cn+4, since the left-hand input comes from one of the AND gates, they continued the use of OR gates, even though it required negating the inputs.

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