As in the pictures, they use different designs (current rate, voltage rate etc. are same.)
What is difference between these two designs?
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As long as the device engages in a "regular" way (at the maximum possible di / dt, minimal dv/dt) and gradually on all the available surface the current it does not really matter. All the "arrangements" are allowed.
The only way to know which is the better "figure" is the "thermal" behavior of the device, shown with IR cameras.
It would be interesting to have "notes" from manufacturers about the "migrations" of impurities which can also have a certain influence on the "life" of the component (and possible destruction) and that the "design" of the connections makes it possible to minimize these "displacements" by "driving" these impurities into "non-essential areas".
See the conclusion (in french) of this "old" note : https://hal.archives-ouvertes.fr/jpa-00217349/document
EDIT : Incidentally, I came across this note ... Infineon Triggering ETT
See paragraph 2.2 for what is called "amplifying gate" ... And conclusion 2.4.