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I have worked with a number of different, high end, image sensors. Several of them have a pedestal or offset voltage. When you cover the camera so no light gets in, you get 600 cts (out of 16384). When you decrease the exposure duration (integration time), you still get 600 cts.

This rules out dark noise (this is leakage current that would be proportional to exposure duration. So what is this offset?

It looks like the amplifier (TIA for a photodiode) has a voltage offset. It is biased before the ADC such that there is always a non-zero voltage.

This type of offset has at least (x2) drawbacks:

  • It consumes dynamic range. You can't use the entire 16384 counts
  • It adds to shot noise (?). That means that I'll always have some shot noise from the electronics that is proportional to the 600 cts?

Questions:

  1. What is the reason for designing the readout electronics to include this voltage offset?
  2. Does it contribute to shot noise?
  3. What is the advantage of this type of design?
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What is the reason for designing the readout electronics to include this voltage offset?

Amplifiers always have some offset. You can try and make it smaller, but it's not going to be zero. Presumably in this case the designer considered the value small enough.

Does it contribute to shot noise?

No, it's just a offset.

What is the advantage of this type of design?

As compared to what? A design with a slightly smaller offset? Possibly they had some reason for not wanting to get too close to zero (e.g. available voltage rails), but it also may not have mattered in this particular design. Often you have more A/D range then you need, in which case a small offset is irrelevant.

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