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I am using a 6 layers PCB with the stack-up configuration shown below, representing only few components there's in the board. A proposed path to the current is shown to be analysed:

enter image description here

QUESTION: When to choose thru vias over blind vias? How to know when there's no need to connect all GND layers with vias? Otherwise, is this needed or even recommended as the great number of components in the board may difficult the analysis for each signal?

The figure shows the return path for the signal that travels around 3 ICs, feel free to comment and correct the circuit analysis thinking of signal integrity, EMI, crosstalk and other PCB concepts.

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    \$\begingroup\$ Are you aware of the cost implications going to blind vias? \$\endgroup\$
    – Kartman
    Oct 4, 2021 at 5:42
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    \$\begingroup\$ Judging from the chart alone, both the power via and the right ground via, could aswell be through-vias without loss in density or efficiency. \$\endgroup\$
    – tobalt
    Oct 4, 2021 at 7:06
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    \$\begingroup\$ @tobalt looks like it would increase the loop area. Is that a concern here? \$\endgroup\$
    – user253751
    Oct 4, 2021 at 15:44
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    \$\begingroup\$ @user253751 one should place the two through-vias close by eachother. \$\endgroup\$
    – tobalt
    Oct 4, 2021 at 16:56
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    \$\begingroup\$ That seems like a silly stack-up. What are you trying to achieve by sandwiching the power plane between two ground planes? And with all those non-signal planes, why are you putting the two signal planes so close together? \$\endgroup\$
    – Sneftel
    Oct 4, 2021 at 18:15

2 Answers 2

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When to choose thru vias over blind vias?

If your design can be completed with only through vias and no blind vias, then that is usually preferred to achieve minimum cost.

If you must introduce blind vias, then you should attempt to minimize the number of different blind via types. For example if doing controlled-depth drilling then prefer to make all blind vias drillable from the top or all blind vias drillable from the bottom to minimize the number of manufacturing steps.

For high speed designs, blind vias may be needed to minimize "stubs" on the RF signal traces. In these instances through vias with back-drilling may be a lower cost alternative.

Blind vias may also be used to enable reducing the board area.

How to know when there's no need to connect all GND layers with vias?

You should always connect all your GND layers with vias. The only question is how many vias and how far apart they may be spaced. 1/10 to 1/8 the wavelength of the highest frequency signal present in your design is a reasonable rule of thumb for the maximum spacing between stitching vias between ground planes.

Otherwise, is this needed or even recommended as the great number of components in the board may difficult the analysis for each signal?

This is not clear. Is what needed?

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  • \$\begingroup\$ I meant to ask when placing a GND via it's recommended to be a thru via across all the GND layers. I'm concerned about choosing a wrong type of via and it cause a reference lost to the signal. \$\endgroup\$
    – Emanuel M
    Oct 4, 2021 at 6:04
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    \$\begingroup\$ If you can fit a through via just use a through via. Use a blind via for ground only if a through via would block routing on other layers. \$\endgroup\$
    – The Photon
    Oct 4, 2021 at 6:07
  • \$\begingroup\$ how to know if a via should be placed conecting only one GND layer or all the GND layers? \$\endgroup\$
    – Emanuel M
    Oct 4, 2021 at 13:46
  • \$\begingroup\$ A via that connects only one layer does nothing at all. If you aren't doing extreme precision analog (14 bit or higher), just connect all the ground layers. \$\endgroup\$
    – The Photon
    Oct 4, 2021 at 14:28
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Blind vias can achieve much higher routing density because they are restricted to one or few layers.

Assuming the typical stackup where layers 1-2, 3-4 and 5-6 are tightly coupled:

whenever your power or signal via crosses between any of the layer 1, 3 or 5, the associated reference layer changes between 2, 4 or 6, respectively. The corresponding ground via has to connect at least to the reference planes before and after the layer crossing.

If your routing and components would require 2 ground vias of different type nearby eachother, e.g. one ground via that has to touch layers 1+2+6 and another which has to touch only 2+4, then these can be combined into one via. I.e. there is no big problem when touching 'unneeded' ground planes..The only drawback is a little bit of common impedance coupling between both return currents routed through that particular via.

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  • \$\begingroup\$ you just answered part of my questions... But how to realize what plane is being used as a reference for each signal? What qualifies a plane to be said it's a ref plane for a signal? \$\endgroup\$
    – Emanuel M
    Oct 4, 2021 at 13:49
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    \$\begingroup\$ @EmanuelM the reference plane is the one that is physically closest to the layer in which your are routing your power or signal line. At high frequency (which is EMI relevant), the overwhelming majority of return current will flow through this nearest plane because that way the current loop is smallest and impedance smallest. If you don't contact this nearest plane with your return path, current has to use a much worse larger loop and will cause EMI trouble. It depends on the stackup which layers are reference to which others, but usually the tightly stacked pairs are: 1&2, 3&4, 5&6. \$\endgroup\$
    – tobalt
    Oct 4, 2021 at 14:45
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    \$\begingroup\$ @EmanuelM stitching vias and return current vias are two different things. Photon wrote a rule of thumb for stitching via density. but for best EMC, place return current vias like you mean it. put them right beside the forward vias and connect the two planes that serve as references to the signal before and after the signal via \$\endgroup\$
    – tobalt
    Oct 4, 2021 at 17:10
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    \$\begingroup\$ well IMO placing stitching vias every 5-10 mm is already rather dense and complicates routing. for EMI a 5 mm loop is still needlessly large..So personally i begin by placing return vias (as through-vias) and then only distribute a few more stitching vias in blank areas of the board. but I have never done a really high density design where i needed blind vias \$\endgroup\$
    – tobalt
    Oct 5, 2021 at 2:31
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    \$\begingroup\$ @EmanuelM I can't tell without seeing the layout of the chips and vias. The L3 power pour often makes sense, but realize that all that low inductance planar capacitance will be choked if you connect it with a one tiny via to the chip. More vias, less impedance is the general rule. \$\endgroup\$
    – tobalt
    Oct 25, 2021 at 12:57

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