0
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I want to try a counter starting from 0 to 12. It can be a simple counter.

always @(posedge clock) begin
        count <= count+1;
        if (count == 4'd12) begin
        counter <= 0;
        end
end

But my task needs skip counting. For example, when skip is 4, count 0-5-10-15-20-25-30, because it's a 4bits counter it should be continue counting as 0-5-10-2-7-12. This skip count can be any number between 0 and 11. How to modify the simple verilog code according to my task?

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18
  • 1
    \$\begingroup\$ Perhaps read this page for some example cases. Or this page for remedial education. \$\endgroup\$
    – jonk
    Oct 4, 2021 at 10:00
  • 1
    \$\begingroup\$ Why not something like this? \$\endgroup\$
    – jonk
    Oct 4, 2021 at 10:37
  • 1
    \$\begingroup\$ When skip is equal to 4, 0-5-10 next won't be equal 12. \$\endgroup\$ Oct 4, 2021 at 10:42
  • 1
    \$\begingroup\$ I can't say that I fully understand your question. You haven't been detailed enough for me in it. So I have to back off at this point until more arrives from you or else someone else clarifies things for me. \$\endgroup\$
    – jonk
    Oct 4, 2021 at 10:45
  • 1
    \$\begingroup\$ wire [3:0] temp = count + 1 + skip; always @(posedge clock) count <= temp >= limit ? temp - limit : temp; \$\endgroup\$
    – Dave Tweed
    Oct 4, 2021 at 11:41

1 Answer 1

0
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Maybe it will be useful to someone.

module Counter(iClk, iRst, iSkip, iRev, oState);
     input iClk, iRst, iSkip, iRev;
   //declare oState:
   //declare internal wires and reg types here:
     output [3:0] oState;
     parameter [3:0] limit = 14;
     reg [4:0] temp = 5'd0;
     reg [4:0] cnt = 5'd0;
     integer skip = 1;

 always @ (posedge iClk)
 begin
  if (!iRst) begin
     
     temp = 5'd0; // to prevent overflow 5bits required
     cnt = 5'd0;
      
  end 
  else begin 
        
        if (iSkip && !iRev) begin // only iSkip asserted
            skip = 5;
        end 
        else if(!iSkip && iRev) begin // only iRev asserted
            skip = -2;
        end
        else if(iSkip && iRev) begin //iSkip and iRev asserted
            skip = 9;
        end
        else begin //Neither asserted
            skip = 1;
        end

        temp = temp + skip;
        
        if (temp > limit) begin
        cnt = temp-limit-1;
        end
        else begin
        cnt = temp;
        end
        
        temp = cnt;
            
        
  end
 end
\$\endgroup\$

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