I am very new to PCB design and have recently completed schematic capture and PCB layout of an optical detection circuit using Altium Designer. My custom PCB consists of a photodiode, transimpedance op amp, 13-bit ADC, and bypass capacitors. This PCB is to be mounted on top of the Arduino Micro via the 17-pin headers, and will interface with the ADC using SPI protocol.

My two questions are:

  • Are there any evident errors with the PCB layout?
  • Are there any evident improvements I can make to the schematic to improve the noise performance?

The current system follows the flow of:
( Photodiode -> Transimpedance Op Amp -> 13-Bit ADC ) -> Arduino Micro -> PC

Design Specifications:

  • Bandwidth: 112kHz
  • 5V Supply to ADC and Op Amp

PCB Specifications (Edited):

  • 2 layer stack
  • Entire bottom layer is a GND plane (polygon pour) that combines analog GND and digital GND (GND traces are 20mils)
  • Within the bottom layer, I have +5V signal traces (25mils) and sensor signal traces (20mils)
  • On the top layer, I have SPI communication lines (20mils)
  • Board dimensions: 48mm x 18mm

2D Top View 2D Bottom View 3D Top View 3D Bottom View PCB Layer Stack Schematic Capture


Reply to @user1850479:

enter image description here

  • \$\begingroup\$ What is your actual question? Try to focus on parts of your design that you want to discuss/improve, be more specific than "Here's everything, I don't know if it works, but can it be better?". \$\endgroup\$
    – Araho
    Oct 4, 2021 at 11:29
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    \$\begingroup\$ This board will be almost impossible to manufacture for a reasonable price. With the 4 different via types you'll have a hard time to find a company and will face up-front costs well beyond 1k€. \$\endgroup\$
    – asdfex
    Oct 4, 2021 at 14:45
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    \$\begingroup\$ Looks to me that there is really no reason not to make this a 2-layer pcb, with all components on the same side (saves time and money). Plus, there's all that extra room... why not use physically larger caps to make hand soldering and rework easier? \$\endgroup\$ Oct 4, 2021 at 15:58
  • 1
    \$\begingroup\$ 4 layers is perfectly fine, the problem are the 3 overlapping blind vias. Just use normal, through vias everywhere. \$\endgroup\$
    – asdfex
    Oct 4, 2021 at 16:05
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    \$\begingroup\$ The question title made me think you were getting warnings/errors from DRC but instead it seems you are seeking review of your design. Perhaps you should edit the title accordingly? \$\endgroup\$
    – JYelton
    Oct 4, 2021 at 16:27

3 Answers 3


4 layers is overkill, but these days it is pretty cheap and it saves time, so no problem with that.

how can I send signals to the middle 2 layers in a 4 stack without the use of vias?

When you use a standard thru via, it goes through all the layers. It will link all the layers where you connect a track to the via, and it will also connect to power/ground planes based on net names.

Your Altium stackup also mentions blind vias, which only connect 2 layers so they leave more space on the other layers. These are much more expensive because they can't be manufactured just by drilling a hole through the whole board, more steps are needed, and these are special order, which means $$$. You don't need blind vias for this project, so make sure the board does not have them, otherwise the PCB fab will not be able to run it through the standard (cheap) process. Just uncheck the "blind/buried" option, I think it's somewhere in the board stackup dialog.

Besides that,

Print it at real size and put your arduino on top of the paper to make sure the pins align correctly.

Tiny 0402 SMD components are a hassle to hand solder, just use 0805.

One pin on each photodiodes is connected to ground, so Altium will automatically connect this thru hole pad to the ground plane. There is no need for an extra ground via.

C1 and C2 should be C0G dielectric, do not use X7R.

Placement and routing of decoupling caps is really bad, long traces should be avoided. Since you have a ground and power plane, just add a ground and power via to the corresponding pins of the opamp. Then you put the decoupling cap on the other side between vias. This will make the traces very short.

Since these opamps are pretty fast, the highspeed part of the feedback network (the cap) should be closest to the opamp, and the resistor is less critical since it has high impedance, a little bit of trace inductance isn't going to change things. So swap the position of R and C.

Putting the resistors on 0.1" headers can be useful for experimenting. Later you can solder the resistors across the header pads.

Also you can use 1µF 16V X7R caps instead of 100nF, they're not expensive.

Using 5V as reference voltage for ADC means its accuracy will depend on the accuracy of 5V from arduino, which is... not very accurate and quite noisy because the micro draws current from it. If a clean noise free reference is important, consider using a reference chip, or a TL431, or just a LDO that won't power any other component so its output will be clean.

  • \$\begingroup\$ Thank you so much for this, if I were to keep the 4 layers and use one layer as a GND plane, is it okay to connect all AGND and DGND to this plane? As well, is having the GND layer span across the entire length and width of the PCB bad in terms of EMI (since there will be routing above and below the traces GND layer )? \$\endgroup\$
    – Kevin
    Oct 4, 2021 at 20:30
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    \$\begingroup\$ Better to not split the ground plane. When ADCs have separate AGND/DGND pins it is to avoid noise on the internal DGND coupling to the internal AGND, but it does not imply you should have 2 ground planes! Clever splits in ground planes is like the old habit that never dies but it also almost never improves things... However, now that you mention it, if you put the opamps on the bottom they will have higher parasitic capacitance with the noisy micro, but if you put them on top with the photodiodes, then the ground plane will act as a shield between micro and analog stuff. \$\endgroup\$
    – bobflux
    Oct 4, 2021 at 20:37
  • \$\begingroup\$ Just finally, would you be able to review the updated layout I have? I edited the main post and included screenshots. If you could point out any errors/bad practices with the current routing or GND plane setup, it would be much appreciated! \$\endgroup\$
    – Kevin
    Oct 13, 2021 at 19:43
  • \$\begingroup\$ Decoupling caps are much better, but there are missing vias on the VCC pin, they show up as unrouted net lines in the picture. The via won't fit in the pad, you can put it under the opamp, connecting directly to the cap. Move the cap if vecessary. \$\endgroup\$
    – bobflux
    Oct 13, 2021 at 20:24
  • \$\begingroup\$ is having the GND plane and signal traces in the same layer bad practice? \$\endgroup\$
    – Kevin
    Oct 13, 2021 at 20:39

Comments on the updated design:

You want to minimize the length of the traces connecting the photodiode to the opamp to the feedback network. Move the opamp closer to the photodiode, even directly over it so that you can eliminate the boxed trace:

enter image description here

Since you are putting components on both sides, consider putting C1/R1 on the backside of the board, directly over the pins they connect. This will depend on how large the photodiode is, but when using TO can diodes I like to lean the edge of the amp off the edge of the can and put the feedback network right up against the can. I then do SMD assembly first and finally solder the TO can. Do this right and you can probably reduce the total amount of trace you have between your components by at least a factor of two, which will greatly reduce parasitics.

Your decoupling capacitors are not connected to the ICs they're decoupling. Probably you forgot the vias. You may also be able to improve the placement. You want the loop from the negative (GND) rail to the positive rail to be as small as possible. Right now you're making that loop bigger by putting the capacitor away from the GND pin. If you move the feedback network to be opposite the opamp, I would bring the capacitor to the same side and put it where you have C2 now. Then route the power trace under the opamp.

Putting signal and ground lines together on 2 layer boards is almost always necessary, and definitely not a bad idea. Don't route through the board unless you have a reason to.

You're not reverse biasing the photodiode. Given the bandwidth, this is probably reasonable, and I did not do any SNR calculations to see if the reduced dark current makes a difference. However it will mean that your photodiode signal will be much less linear with intensity, especially under bright conditions. Make sure you're ok with that.


Here is the current loop in your most recent design:

enter image description here

That is much bigger than it needs to be because you are routing above and below the chip for no reason. Here is a smaller loop:

enter image description here

See how the current now encloses a much smaller area? That is means lower inductance and better decoupling. You might choose to make the loop larger to avoid putting parts on the backside, but even then you can do much better than you had by not putting the capacitor way out of the way on the top.

Also, since you're thinking of using the USB+5 as your reference voltage (which is not a great idea since your performance will be strongly dependent on the noise present in each USB host), you probably want to give yourself a pad for a resistor between +5 and the Vref pin and definitely increase that capacitor to at least 1 uF, preferably 10uF. Try maybe 100 ohms, which reduces your Vref to ~4.99V (+/- 0.25v for USB) and gives a low pass cut off at 159 Hz.

  • \$\begingroup\$ Must the decoupling capacitor be closer to the voltage supply pin to be fully in effect? Or must the capacitor be closer to the ground pin? \$\endgroup\$
    – Kevin
    Oct 14, 2021 at 4:15
  • \$\begingroup\$ In addition, I don't understand how the photodiode is not reverse biased? The anode of the photodiode is closer to ground on the schematic, and the PCB was generated directly from the schematic. Worst case, I can just solder the photodiode accordingly? \$\endgroup\$
    – Kevin
    Oct 14, 2021 at 4:16
  • \$\begingroup\$ @Kevin A bias is a voltage you apply to the diode. Right now you have both ends at zero volts, so there is no bias. It does not matter which pin the capacitor is closest to, only the size of the loop formed by the circuit. \$\endgroup\$ Oct 14, 2021 at 5:00
  • \$\begingroup\$ Thank you. I updated the layout again according to your advice. GND and +5V are now on the bottom plane and I tried to minimize trace length as much as possible. This time, there are more vias for the feedback resistors/capacitors of the opamp and the decoupling cap for the ADC. The design rule shows no indication of unrouted components. Please let me know if you observe anything else to be improved! \$\endgroup\$
    – Kevin
    Oct 14, 2021 at 16:53
  • \$\begingroup\$ @Kevin TIAs look much better. The ADC decoupling is still a bit weird. The board has analog and digital ground. You want to decouple with a short loop from Vref to AGND and a short loop from VDD to DGND. Put C5 on the opposite side right up against the pins. Don't share vias between C5 and C6 since they have different currents (analog vs digital) even if the different GNDs are connected. \$\endgroup\$ Oct 14, 2021 at 19:10

For manufacturability, don't put those vias between pins 3/4.

FWIW, to keep the power clean I would put a series L or ferrite in series to create an analog supply for the op amps. You could also have divided grounds by splitting the plane. In Altium this can be done with polygons or by drawing lines on the negative plane layer if you used that. The ground would be joined at the pin, or even using one of the pins instead of the other. This would keep you SPI noise out of the amps and ADC better.

The TI amp looks right to me, here is a similar example: https://youtu.be/0b9Rt8rd5-8?t=434

  • \$\begingroup\$ Are you referring to the vias placed directly on top of the pins of the OpAmp or ADC? \$\endgroup\$
    – Kevin
    Oct 14, 2021 at 18:57
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    \$\begingroup\$ @Kevin Both. For hand soldering what you are doing is fine, but for automated assembly putting vias in pads can result in solder wicking down, resulting in inconsistent solder joints. If you are having 1000 of these made, just move the via out of the pads to be safe. If you're doing it by hand then it makes no difference. \$\endgroup\$ Oct 14, 2021 at 19:19
  • \$\begingroup\$ @gcycle7 Thank you for the notice, though with time constraints, I will leave the external analog supply and regulation as a future improvement. I've moved the vias away from the pins, would you be able to finally check over the layout? \$\endgroup\$
    – Kevin
    Oct 15, 2021 at 17:04

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