Altium Designer PCB Layout Review

Question

I am very new to PCB design and have recently completed schematic capture and PCB layout of an optical detection circuit using Altium Designer. My custom PCB consists of a photodiode, transimpedance op amp, 13-bit ADC, and bypass capacitors. This PCB is to be mounted on top of the Arduino Micro via the 17-pin headers, and will interface with the ADC using SPI protocol.

My two questions are:

• Are there any evident errors with the PCB layout?
• Are there any evident improvements I can make to the schematic to improve the noise performance?

The current system follows the flow of:
( Photodiode -> Transimpedance Op Amp -> 13-Bit ADC ) -> Arduino Micro -> PC

Design Specifications:

• Bandwidth: 112kHz
• 5V Supply to ADC and Op Amp

PCB Specifications (Edited):

• 2 layer stack
• Entire bottom layer is a GND plane (polygon pour) that combines analog GND and digital GND (GND traces are 20mils)
• Within the bottom layer, I have +5V signal traces (25mils) and sensor signal traces (20mils)
• On the top layer, I have SPI communication lines (20mils)
• Board dimensions: 48mm x 18mm

Datasheets:

• Photodiode: https://www.vishay.com/docs/81519/bpw21r.pdf
• Op Amp: https://www.digikey.ca/en/products/detail/texas-instruments/LMP7717MAE-NOPB/2092434
• ADC: https://ww1.microchip.com/downloads/en/DeviceDoc/21697F.pdf

Reply to @user1850479:

Answer 1

4 layers is overkill, but these days it is pretty cheap and it saves time, so no problem with that.

how can I send signals to the middle 2 layers in a 4 stack without the use of vias?

When you use a standard thru via, it goes through all the layers. It will link all the layers where you connect a track to the via, and it will also connect to power/ground planes based on net names.

Your Altium stackup also mentions blind vias, which only connect 2 layers so they leave more space on the other layers. These are much more expensive because they can't be manufactured just by drilling a hole through the whole board, more steps are needed, and these are special order, which means $$$. You don't need blind vias for this project, so make sure the board does not have them, otherwise the PCB fab will not be able to run it through the standard (cheap) process. Just uncheck the "blind/buried" option, I think it's somewhere in the board stackup dialog.

Besides that,

Print it at real size and put your arduino on top of the paper to make sure the pins align correctly.

Tiny 0402 SMD components are a hassle to hand solder, just use 0805.

One pin on each photodiodes is connected to ground, so Altium will automatically connect this thru hole pad to the ground plane. There is no need for an extra ground via.

C1 and C2 should be C0G dielectric, do not use X7R.

Placement and routing of decoupling caps is really bad, long traces should be avoided. Since you have a ground and power plane, just add a ground and power via to the corresponding pins of the opamp. Then you put the decoupling cap on the other side between vias. This will make the traces very short.

Since these opamps are pretty fast, the highspeed part of the feedback network (the cap) should be closest to the opamp, and the resistor is less critical since it has high impedance, a little bit of trace inductance isn't going to change things. So swap the position of R and C.

Putting the resistors on 0.1" headers can be useful for experimenting. Later you can solder the resistors across the header pads.

Also you can use 1µF 16V X7R caps instead of 100nF, they're not expensive.

Using 5V as reference voltage for ADC means its accuracy will depend on the accuracy of 5V from arduino, which is... not very accurate and quite noisy because the micro draws current from it. If a clean noise free reference is important, consider using a reference chip, or a TL431, or just a LDO that won't power any other component so its output will be clean.

Answer 2

Comments on the updated design:

You want to minimize the length of the traces connecting the photodiode to the opamp to the feedback network. Move the opamp closer to the photodiode, even directly over it so that you can eliminate the boxed trace:

Since you are putting components on both sides, consider putting C1/R1 on the backside of the board, directly over the pins they connect. This will depend on how large the photodiode is, but when using TO can diodes I like to lean the edge of the amp off the edge of the can and put the feedback network right up against the can. I then do SMD assembly first and finally solder the TO can. Do this right and you can probably reduce the total amount of trace you have between your components by at least a factor of two, which will greatly reduce parasitics.

Your decoupling capacitors are not connected to the ICs they're decoupling. Probably you forgot the vias. You may also be able to improve the placement. You want the loop from the negative (GND) rail to the positive rail to be as small as possible. Right now you're making that loop bigger by putting the capacitor away from the GND pin. If you move the feedback network to be opposite the opamp, I would bring the capacitor to the same side and put it where you have C2 now. Then route the power trace under the opamp.

Putting signal and ground lines together on 2 layer boards is almost always necessary, and definitely not a bad idea. Don't route through the board unless you have a reason to.

You're not reverse biasing the photodiode. Given the bandwidth, this is probably reasonable, and I did not do any SNR calculations to see if the reduced dark current makes a difference. However it will mean that your photodiode signal will be much less linear with intensity, especially under bright conditions. Make sure you're ok with that.

Edit

Here is the current loop in your most recent design:

That is much bigger than it needs to be because you are routing above and below the chip for no reason. Here is a smaller loop:

See how the current now encloses a much smaller area? That is means lower inductance and better decoupling. You might choose to make the loop larger to avoid putting parts on the backside, but even then you can do much better than you had by not putting the capacitor way out of the way on the top.

Also, since you're thinking of using the USB+5 as your reference voltage (which is not a great idea since your performance will be strongly dependent on the noise present in each USB host), you probably want to give yourself a pad for a resistor between +5 and the Vref pin and definitely increase that capacitor to at least 1 uF, preferably 10uF. Try maybe 100 ohms, which reduces your Vref to ~4.99V (+/- 0.25v for USB) and gives a low pass cut off at 159 Hz.

Answer 3

For manufacturability, don't put those vias between pins 3/4.

FWIW, to keep the power clean I would put a series L or ferrite in series to create an analog supply for the op amps. You could also have divided grounds by splitting the plane. In Altium this can be done with polygons or by drawing lines on the negative plane layer if you used that. The ground would be joined at the pin, or even using one of the pins instead of the other. This would keep you SPI noise out of the amps and ADC better.

The TI amp looks right to me, here is a similar example: https://youtu.be/0b9Rt8rd5-8?t=434