Is it OK to control many (10s) of analogue switches with a single buffered op-amp?

Question

Analogue Switch (SPDT) - DG419LEDY-T1-GE4 Datasheet: Vishay - DG41XLE Analogue Switches
Op-amp - LM358PT Datasheet: LMX58 Op-amps

Using a microcontroller's GPIO, and a non-inverting buffered op-amp output (LM358), I will be controlling the analogue switch mentioned above. Vcc of both the op-amp and the analogue switch is 12V.

I tested this on a breadboard with 3 switches and only the micro's GPIO at first, but saw that the output high voltage of 3.28V had dropped to about 3.05V. So I added the buffered op-amp stage and that resolved it. I don't have enough switches to do more testing, but I plan to be using about 27 in total, maybe a few more.

1. Should I add more op-amp stages for better load distribution? Maybe 3 op-amps handling 9 switches each?

• Page 3 of the switch's datasheet says the max. input current draw is 1µA. So a total draw of about 30µA.
• Page 7 of the op-amp's datasheet says the typical output source current is about 40mA, albeit that's for a Vcc of 15V and a lower output voltage. But 10s of µA for the switches vs. 10s of mA for the op-amp really shouldn't be an issue for the op-amp is my thinking.
• ...but 3 switches had a non-negligible effect on the GPIO output, which is rated to source upto 15mA at most. So why did this happen?

2. The micro will be driving the output at its slowest setting, and there will be no high rate of back and forth switching going (maybe switched back and forth once or twice an hour)

• Would a single 100nF decoupling capacitor suffice for each op-amp's supply rail in practice?
  With a peak current draw of 30µA, a 0.6V/µs slew rate for the op-amp (5.5µs rise time to 3.3V), and assuming a bad power-supply ripple of 100mV:
  Then the required capacitance is (30µA x 5.5µs)/0.1V = 1.65nF

• The switches will all trigger at once.

Schematic below, note a number of pins are still not connected as it's in progress, and only a single switch is shown.

Answer 1

If your speed requirements are modest, this op amp should drive millions of these switches. The capacitive load would eventually start to affect stability, though. Not sure why the loading affected the gpio that significantly...are you sure it's rated to source 20mA, and that it's not in open drain mode or something?

Any reason you're not using a comparator or digital buffer to boost this signal? An op amp seems like overkill, as it's not even analog.

Answer 2

I think the fault lies elsewhere, because those switch inputs are CMOS logic inputs, they sink almost no current. You can drive them directly with GPIO outputs. Without a buffer, even if there are 10s of them in parallel.

The table is taken from a DG419 from Maxim, but these parts are pretty well standardized so, I wouldn't expect any appreciable differences.

Another thing: If your DG419 has a \$V_L\$ pin, don't leave it floating but connect it to the VDD of the GPIO ( or atleast a permanently high GPIO pin).