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I have been using Xilinx FPGA devices for a while and I use HLS extensively to create parts of my design.

I have currently switched to Actel FPGA devices and specifically the ProASIC3 family, and wanted a similar functionality like HLS (Embedded C or custom IP design feature), for the Libero and SynplifyPro tool and was not able to find such a feature, thus making me handicapped.

Any ideas or workarounds on making HLS like feature exist in Actel FPGA programming as well?

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    \$\begingroup\$ doesn't Vivado HLS translate that "custom C" into usable VHDL at some stage? \$\endgroup\$ Oct 6, 2021 at 12:21
  • \$\begingroup\$ Yes it does convert it. It is converted at the stage when the IP is generated out of the user written C code and testbench. My question is that "Is there any converters and tools for doing high level synthesis on the actel devices"? \$\endgroup\$ Oct 6, 2021 at 12:34
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    \$\begingroup\$ You also asked about workarounds. Using VHDL may be a workaround. (I make no claims that the licensing of either toolset permits it, nor that the auto-generated VHDL is actually usable). However, you will probably find that simply using VHDL (which is designed for hardware synthesis) is actually easier than using some bastardised C (which is not). The trick is to use VHDL at a higher level than most teaching materials do. \$\endgroup\$ Oct 6, 2021 at 12:35

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There is a tool for working on High level synthesis and write C like code that gets transformed to verilog/vhdl code. The tool is called SmartHLS by Microsemi.

Smart HLS user guide

It is eclipse based dev environment and can be integrated with libero.

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  • \$\begingroup\$ HLS is only supported for IGLOO, Polar and SmartFusion devices. There goes my dream of programming ProASIC chip using HLS. \$\endgroup\$ Oct 21, 2021 at 13:51

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