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I am using the pynq board for developing FPGA code for an application. For communication with the PC I am using the ethernet port given on the pynq board. By default the ethernet port is configured to the PS(Cortex processing system), which is on the same fabric as the zynq.

For my application, I need the data communication to happen directly with the FPGA. For that I have referred to this github repo from Xilinx. Xilinx resource pynq networking

I want to be able to interface directly with the FPGA without an overlay written. Is there a way to do this?

From the pynq schematic, there are dedicated MIO lines for the ethernet. enter image description here

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    \$\begingroup\$ The PS MIO is connected only to the PS. While there "may" be a way to use the central interconnect, I think you'll find that there are easier ways to do what you want. An example is to dma data to/from ram and use the ps network stack to handle ethernet. \$\endgroup\$
    – johnnymopo
    Oct 6, 2021 at 15:41
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    \$\begingroup\$ "Ethernet" has a broad meaning in your question. What level of function/layers do you want to implement in the FPGA? Whatever you do, upper level protocols are highly algorithmic and processing intensive. Thus, it is much easier to implement in processors. \$\endgroup\$
    – jay
    Oct 6, 2021 at 15:41
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    \$\begingroup\$ Thanks for the directions @jay, it is much better to implement the ethernet on the processor and then relay the data to the FPGA. Thanks for the DMA idea @ johnnymopo . \$\endgroup\$ Oct 7, 2021 at 6:06
  • \$\begingroup\$ I am trying to make an overlay which bridges the ethernet data at the processor to the FPGA. Any idea on what things need to be taken care of when implementing an overlay? \$\endgroup\$ Nov 2, 2021 at 8:17

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