Creating a digital PLL

Question

I want to drive a quartz crystal resonator at its resonant frequency so I need to stay locked on to its resonant frequency as its resonant frequency changes. I'm using an FPGA to do this.

I want to use a PLL to stay locked on to the resonant frequency. My quandary is, how do I capture and compare the phase shift that occurs when the resonant frequency changes?

Suppose my setup is like this:

A normal PLL loop looks like this:

I would assume that in the typical PLL loop, my "VCO" is the DDS (since the frequency output of the DDS is determined by a constant value input just like a DC signal controls an AC output of a VCO) and the "reference signal" would be the response signal of the resonator (ie. the desired frequency).

Now suppose at time = 0 I know what the resonant frequency is (maybe I found it by doing a frequency sweep and looking for amplitude response). Then, some time later, the resonant frequency changes.

The "new" resonant frequency would cause the "old" frequency to phase shift. But how would I quantify this?

Typical methods involve comparing the signals in the time domain which would mean I would somehow need to save one period of the "old" frequency I'm driving the resonator at and then "overlay" that with the correct period in time with the "new" phase shifted signal such that the phase difference is apparent (they must be synchronized).

My design would look like this:

This seems very convoluted and I believe I'm overcomplicating things.

Answer 1

You don't need a PLL, rather you need a series and parallel oscillator and, you must choose which mode is preferable.

It could also be an Injection Locked Loop which could be an offset biased and forced oscillation with mutual coupling, and is a common phenomena of nature.

Your resonant frequency will change with every environmental variable from temperature, pressure, vibration, shock, and equivalent parasitic capacitance and equivalent inductance ESL.

When you make an oscillator, you can easily measure f, and tune it with a known C. It can be pulled or drift within in the BW determined by Q and possible a harmonic with a known capacitance and gain to satisfy the Barkhausen criterion of >=1 loop gain at 0 Deg.

The above is a simulation of the impedance ratio of a 1kHz resonator similar to any Piezo or Xtal resonators. fs= 969 Hz, fp= 1.02 kHz . By adding reactance, one could tune the frequency to exactly 1.000 kHz, if you wanted or make it into an oscillator.

• Higher voltage low current, or high current low voltage where current is proportional to force like ultrasonic exciters.

• Series mode is in phase or 0 deg. and parallel mode is anti-phase or 180 deg., and thus requires an inverter to oscillate with negative feedback for DC as well to self-bias.

• Series mode requires a low source impedance to drive it.

• The Qs in series mode is \$Q_s= \dfrac{X_{(\omega_0)}}{R~~~~~}= \dfrac{\omega_0 L}{R} = \dfrac{1}{\omega_0 RC}\$

• The Qp in parallel mode is the inverse, \$Q_p=\dfrac{R~~~~}{X_{(\omega_{_0)}}}=\dfrac{R}{\omega_0 L} = {\omega_0 RC}\$

• also damping factor \$\zeta=\dfrac{1}{2Q}\$

Q is relevant to all harmonic and oscillatory behaviours from an electron to a gyrotron to a piezo crystal to a structural resonance to an RF induction heater.

Q is also defined by the impedance ratios to determine the resonant frequency to the half-power full bandwidth, BW ratio.

How you choose to oscillate your high Q resonant material depends on your expectations and assumptions or to be defined, (TBD) "SPECS"

i.e. Define your specs then a simple solution is possible.

But you don't need a complex PLL, although that is possible, if you have a signal from the resonating signal and a mixer that shifts the phase by 90 deg or 180 deg or 360 deg, by design.

The simplest solution for a sinusoidal Hartley Oscillator using a 6 MHz Series Xtal is as follows. If you need lower harmonic content or higher voltage or lower impedance, then you need a spec. for V, Z, f, tolerances, bias etc.

But if you only need it to oscillate, this is all you need.

Changing the 150 pF ratios can amplify the signal to 10Vpp. I chose std values for a 6 MHz series Xtal.

Answer 2

Assuming you want to see a large signal amplification in your resonator, you need to load it so that its unloaded Q is dominating the loaded Q. That means that losses in the resonator dominate losses in the drive and sense impedances.

You either need to drive and sense from short circuits, or from open circuits. Which is easier to do will depend on the impedance level, Q and frequency of your resonator, which you haven't disclosed. That's for an LC resonator where you get the choice of configuring it in series or parallel. For a mechanical resonator, you may be stuck with just one choice.

If you choose short circuits, then a voltage output DDS is easy. You'd sense the current at the ADC with either a virtual ground amplifier, or a very small resistor to ground that you sense the voltage across. If you choose open circuits, then a high impedance buffer for the ADC is easy, and you'd need to current drive from your DDS, either making a high impedance active current drive like a Howland, or an open collector, or simply a high value resistor in series with a voltage source.

When a resonator is in resonance, the voltage across and current through are in phase.

So now the PLL is straightforward. Pick a drive frequency. Measure the current phase with respect to drive phase. Adjust the drive frequency up or down, rinse and repeat until you get zero phase.

The response to a change in frequency will be slow, and the higher the Q of the device, the slower it will be. This places an unavoidable lowpass filter in the loop. For loop stability, you need to arrange for the loop bandwidth to be somewhat less than this.

Answer 3

^{simulate this circuit – Schematic created using CircuitLab}

What you call it PID is actually a compensator, PI like. You do measure voltage and current and compare their phases.

But this circuit would be too complex, you could simplify it by making a zero cross detectors for voltage and current.

^{simulate this circuit}

In All Digital PLL (ADPLL) the phase detector measures pulses, not analog values. It's much simpler and robust than using ADC. Further you can add a digital lag to compensate the voltage/current measurement phase difference

EDIT:

^{simulate this circuit}

Note, that you don't even need a DDS and the analog amplifier for resonant circuit, a H-bridge is enough. You can find similar implementations in inductive heating furnaces, resonant Tesla coil drivers. They all have one issue, at the light load it would blow off due to accumulating energy. So there are many techniques to avoid this by skipping some periods or modulating the output with Enhanced Pulse-Density-Modulation (EPDM).