I'm working on an FPGA and I have implemented a component that can take a clock and dynamically change the phase. Now I think there are some problems with this component because the target of the clock is not responding correctly. The clock is a 150 MHz clock.

My first thought was to use my scope to measure the phase between the original and shifted clock using an oscilloscope after I wire them to output pins. But my oscilloscope is not good enough to measure at this speed. So I started looking online, exploring whether I could build or buy something that could measure the phase.

This led me to the AD8302 IC. From my limited understanding, this should be able to do what I want. E.g. I can buy a breakout PCB and hook up the original and shifted clock to the SMA connectors and then read out vphs.

Is my idea of what to do correct/feasible? If not, what approach should I take? I'm just a hobbyist, so I don't have access to expensive equipment.

  • \$\begingroup\$ Do you derive the shifted clock with a PLL? Does it drive external or internal logic? Do you have compensation for the delay of the downstream connection? \$\endgroup\$ Oct 7, 2021 at 20:06
  • \$\begingroup\$ If I read the datasheet correctly, that's a 50Ω input part for RF. Can your circuit drive 50Ω? \$\endgroup\$
    – Aaron
    Oct 7, 2021 at 20:13
  • \$\begingroup\$ @aaron I did not consider this. I don't think so. It's an fpga with a maximum drive strenght of 8mA at 3.3v :/. would it be possible to use transistors to up the drive strength? \$\endgroup\$
    – John Smith
    Oct 8, 2021 at 12:25
  • \$\begingroup\$ @SimonRichter Yes both the original clock and shifted clock are derived from a PLL. One clock will drive internal logic the other external. \$\endgroup\$
    – John Smith
    Oct 8, 2021 at 12:26
  • \$\begingroup\$ I wonder if you could apply Time Difference of Arrival (TDOA) to solve this? Using a signal that switches around 600Hz-1kHz, alternate sampling both signals and mix them. If they are out of phase it creates a beat frequency that can be measured, if they are in phase you get a null signal. theleggios.net/wb2hol/projects/rdf/tdoa2.htm \$\endgroup\$
    – Aaron
    Oct 9, 2021 at 17:50

2 Answers 2


Assuming that both clock waveforms are the same, all you need to measure clock difference is a wideband AC voltmeter: just measure between the clocks. At 0 degrees phase shift you get 0V differential voltage, at 180 degrees you get some maximum value (~V_hi at very low frequencies, less as you go past 1MHz).

A wideband AC voltmeter can be a simple demodulator probe - see e.g.this example. To get the sensitivity down to 0V, you'll need to offset one of the waveforms "down", but this is easy to do since the offset voltage can be a scaled voltage from a 3V coin lithium battery. For example:


simulate this circuit – Schematic created using CircuitLab

The voltmeter is a DC voltmeter (e.g. multimeter). L1 and L2 can be parts designated as RF chokes, their power rating is not important since there'll be negligible DC currents flowing through them. You may have better results with slightly smaller or larger chokes, depending on their parasitics. I'd try several values between 1-100uH with 180 degree out-of-phase clocks (i.e. one output inverted), and select for highest DC voltage reading. Do not assume anything about the chokes, i.e. test every pair you have, rather than stopping - parasitics are important, and you may get several local sensitivity maxima.

To adjust zero: connect CLK1 to CLK2 (of course no FPGA connection). Adjust for a slightly positive voltage, e.g. 0.01V on mV scale. Then connect CLK1 and CLK2 to two otherwise identical FPGA outputs. The voltmeter will read close to the zero-adjusted voltage when the clocks have no phase offset. Small phase offsets will be detectable in, say, 300mVDC range on the multimeter. With VIO at 3.3V, you'll get 10-20 degrees of phase shift full scale.

The zero voltage should be adjusted each time the chokes are changed, before taking further voltage readings.

I've laid the circuit out symmetrically as far as practical, to aid in linearity. It'll help to keep this arrangement on the perfboard, or even just laid out over a small copper laminate used as the ground plane. I wouldn't bother with a solderless breadboard.

It is very important that both clocks come from output pins on the FPGA, so that they are driven with identical driver circuits. Do not take one clock directly from the oscillator. Use two dedicated outputs, configured for highest drive strength available.

Most voltmeters have high impedance (10MOhm for typical multimeters), so that's why there's a discharge resistor R2 across C6.


Simple option: Make an XOR of the two clock signals and put it out on another pin from the FPGA. Low pass filter the output with an RC network and measure the DC voltage.

Assuming the output pin swings 0V to Vcc:

0V = no phase difference at the input of the XOR

Vcc/2 = +/-90 degrees

Vcc = 180 degrees

Similar phase detector response as the AD8302, similar phase ambiguity.

I'd expect it to operate roughly ideally around +/- 90 deg, with operation nearing the rails dependent on rise times and actual timing response of the gate. If you want precision, use an XOR like the HMC745

Another possibility is the phase/frequency detector like the HMC439. As this is intended for use in a PLL, the measured phase difference is called the error voltage: enter image description here

It has the response you want, and is very linear and no 180 deg phase ambiguity that the XOR type detectors have.


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