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Due to the chip shortage, I'm trying to perform timing analysis of an existing CPLD design for a number of alternative chips from different manufacturers.

I have existing hardware description source code (VHDL) and I/O timing specifications (SDC). The CoolRunner-II CPLD family isn't supported by Vivado so I'm using ISE.

Adding VHDL files to a design is easy. I don't have any pin assignments yet, because I'm still evaluating which CPLD parts are worth going through place-and-route with my PCB team, so I'll let the fitter auto-select pin assignments for now. But where do I tell ISE to read SDC timing constraints from a text file?

I've found numerous mentions of SDC and XDC constraints on the Xilinx site and documentation of the individual commands, but none of the documentation I've found has covered step #1 -- how to pass an SDC file to the synthesis tool.

I'm not looking for a way to input timing constraints graphically, or use an alternate constraint language such as UCF. SDC is the standard vendor-independent timing language and I already have the constraints written.

Is it possible to pass SDC constraints to the ISE synthesis tools? Do I need to upgrade from WebPack to a paid license? What steps do I go through in ISE to add an SDC file to the project and use it for timing analysis?

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  • \$\begingroup\$ AFAIK, you can only use .sdc files with Synplify synthesis, not with ISE synthesis. If you're using ISE synthesis, then you'll have to find or create a way to translate .sdc to .ucf or .xcf I've never seen such a tool -- most are oriented toward forward migration, in the other direction. \$\endgroup\$
    – Dave Tweed
    Oct 11, 2021 at 15:54
  • \$\begingroup\$ @DaveTweed I saw some information to that extent but I haven't been able to exactly figure out the relationship between Xilinx ISE and Synplify. I'm using ISE in the sense of "ISE Design Suite" not a single tool in that suite. Are XST and Synplify two different synthesis tools within the Xilinx Design Suite eco-system, or is Synplify a paid third-party tool with support for Xilinx devices and integration with the ISE-provided programmer etc? \$\endgroup\$
    – Ben Voigt
    Oct 11, 2021 at 16:40
  • \$\begingroup\$ What confuses me is that there are multiple third-party tools that support Xilinx parts (Aldec, Synopsys, Mentor, etc) but use of Synplify is detailed in Xilinx's own documentation. \$\endgroup\$
    – Ben Voigt
    Oct 11, 2021 at 17:21
  • \$\begingroup\$ Synplify is a Synopsys product. I think it was basically the only 3rd-party synthesis tool that Xilinx officially supported at the time, which is why the information about .sdc files appears in the Xilinx User Guides related to timing analysis. I can find nothing in the User Guides that indicates that .sdc files can be used with anything other than Synplify. \$\endgroup\$
    – Dave Tweed
    Oct 11, 2021 at 17:27
  • \$\begingroup\$ @DaveTweed: Thanks! Sorry for asking what seems to be such a basic question but after seeing (and using) Modelsim Altera Edition (Lite), Modelsim Altera Edition, Modelsim Modelsim Intel Edition, Modelsim Intel Edition (Lite), Xilinx Edition (Lite), Mentor Modelsim (Lite) etc I can no longer assume that a product described in the vendor documentation is referring to the popular separately-sold third-party product having that name. \$\endgroup\$
    – Ben Voigt
    Oct 11, 2021 at 17:35

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AFAIK, you can only use .sdc files with Synplify synthesis, not with ISE synthesis. If you're using ISE synthesis, then you'll have to find or create a way to translate .sdc to .ucf or .xcf I've never seen such a tool -- most are oriented toward forward migration, in the other direction.

Synplify is a Synopsys product. I think it was basically the only 3rd-party synthesis tool that Xilinx officially supported at the time, which is why the information about .sdc files appears in the Xilinx User Guides related to timing analysis. I can find nothing in the User Guides that indicates that .sdc files can be used with anything other than Synplify.

ISE is really a collection of command-line tools that are more-or-less tied together by the provided GUI. Each step of the process can be run individually, or a 3rd-party tool can be substituted in some cases.

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