In the following video on SR latch (from University of Illinois) on youtube http://www.youtube.com/watch?v=CUfZladDqq8 ,

(The point illustrated in this composite screenshot!)


The "instructor" says the following 1mn 10 seconds into the main video --"Let's change S to 0(from 1),then with S and R as 0, both Q and Q' will hold their values"--Well that's what I don't get!!Now please try to see through the following clumsy description of my doubt and clear my confusion (I am a computer science student and this course is new for me,so please bear with me) :

How will Q and Q' hold their values?I mean, we are assuming that Q,which is fed as input to the bottom NOR gate,DOESN'T CHANGE IF S IS CHANGED FROM 1 TO 0!!!I completely don't get it.Isn't Q dependent on(is a function of) S and should change the moment S changes?I mean,S determines the value of Q'(For example S has to be 1 for Q' to be 0),and Q' in turn determines the value of Q.So, doesn't it mean it depends on S? Shouldn't Q change the moment S changes? You see, as per what I have studied so far, if there is a single logic gate, then we expect the output to be dependent on the inputs, and we expect it to change the moment any input changes, ISN'T IT?We don't expect the output to stay the same (or hold its value) if the inputs that determine it change.Then how come in the SR latch we expect the output Q of the upper NOR gate to hold its value when S changes from 1 to 0? Isn't it ironic that we automatically assume Q to remain the same(preserve its value) while the whole point of designing the SR latch is to preserve a value? Let me explain further.

Say in our circuit we use a voltage range of 0-2V to refer to 0(low) and a voltage range of 3-5V to refer to 1(high).So when we expect Q to be logical 1 or 3-5 Volts even after the input S that determines it changes, do we expect "SOMETHING" to hold that 3-5 volts of Q?What holds it?Is there somekind of ELECTRICAL REMNANCE,LATENCY or STORAGE involved?Or S changes much faster than Q could change!I am so utterly confused.I could just remember the whole thing by rote without understanding it, but I don't want to do that.So please answer what's up.I am sure you got what I mean to ask.The bottomline being---"S determines Q' which in turn determines Q, so when S changes, I expect Q to change or to be in an undefined state as the input indirectly determining it has changed.I just don't get why the instructor IMPLICITLY ASSUMES Q WILL STILL BE 1 when S changes to 0.

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    \$\begingroup\$ Why the shouting? \$\endgroup\$ – user17592 Feb 24 '13 at 13:40
  • \$\begingroup\$ First time and first question on this forum, so please bear with me this time.Once I learn how to highlight some lines, I will stick to the etiquette instead of using Caps.I apologize. \$\endgroup\$ – T Singh Feb 24 '13 at 13:41
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    \$\begingroup\$ There is no problem if you just take some time to read a little on the editing help and to edit your question. 'Seasoned contributors' aren't there to layout your question. \$\endgroup\$ – user17592 Feb 24 '13 at 13:46
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    \$\begingroup\$ @CamilStaps I appreciate you giving advice, but lets try to be friendly, often someone stuck on a problem is not going to want to address learning the site that moment. They will take some time and minor edits by you will both earn you a badge and make their first experience more hospitable. \$\endgroup\$ – Kortuk Feb 24 '13 at 16:31
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    \$\begingroup\$ I can excuse some usage of caps. The real problem here is extreme verbosity and generally a lack of focus. I tried salvaging the question, but halfway through I couldn't remember what point the question was trying to make. \$\endgroup\$ – Chris Laplante Feb 24 '13 at 18:09

The point you're missing is the fact that once the Q output has gone high, the output of the gate that S is connected to is forced low, regardless of whether S remains high or subesquently goes low. In other words, once that happens, the output of that gate is no longer dependent on the value of S.

By symmetry, the same can be said of the R input. Once it goes high, the Q output is forced low, and as long as S is also low, the Q' output goes high. At that point, the value of R no longer matters, and it can go high or low without affecting the state of the latch.

  • \$\begingroup\$ I don't know why caps are assumed to be shouting, but every netiquette guide I've ever seen mentions it: a, b, c, d, e, f, etc. \$\endgroup\$ – davidcary Feb 24 '13 at 15:23
  • \$\begingroup\$ Out hours back to the days when the only don't you had was decided for you by what model VT terminal you were using and all-caps was the only way to add emphasis. But some users still had habits from the time when lower case letters were considered an unnecessary luxury, so continued to write all-caps. \$\endgroup\$ – The Photon Feb 24 '13 at 16:31
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    \$\begingroup\$ s/don't/ font ... \$\endgroup\$ – The Photon Feb 24 '13 at 16:32

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